M306V7MG_15 Datasheet, PDF (146/300 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER

M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
S Slave address R/W A Data A Data A/A P
7 bits
“0”
1 to 8 bits
1 to 8 bits
(1) A master-transmitter transmits data to a slave-receiver
S Slave address R/W A Data A Data A P
7 bits
“1”
1 to 8 bits
1 to 8 bits
(2) A master-receiver receives data from a slave-transmitter
S
Slave address
1st 7 bits
R/W
A
Slave address
2nd byte
A
Data
A Data A/A P
7 bits
“0”
8 bits
1 to 8 bits
1 to 8 bits
(3) A master-transmitter transmits data to a slave-receiver with a 10-bit address
S
Slave address
1st 7 bits
R/W
A
Slave address
2nd byte
A
Sr
Slave address
1st 7 bits
R/W
Data
A
Data
A
P
7 bits
“0”
8 bits
7 bits
“1” 1 to 8 bits
(4) A master-receiver receives data from a slave-transmitter with a 10-bit address
1 to 8 bits
S : START condition
A : ACK bit
Sr :Restart condition
P : STOP condition
R/W : Read/Write bit
Fig. 2.11.41 Address data communication format
From master to slave
From slave to master
(13) Precautions when using multi-master I²C-BUS interface i
s BCLK operation mode
Select the no-division mode and set the main clock frequency to f(XIN) = 16 MHz or 10 MHz.
In this case, make sure the Peripheral Mode Register (address 027D16) bit 7 is set according to
the frequency.
s Used instructions
Specify byte (.B) as data size to access multi-master I²C-BUS interface i-related registers.
s Read-modify-write instruction
The precautions when the read-modify-write instruction such as BSET, BCLR etc. is executed for
each register of the multi-master I²C-BUS interface are described below.
•I²Ci data shift register (IICiS0)
When executing the read-modify-write instruction for this register during transfer, data may
become a value not intended.
•I²Ci address register (IICiS0D)
When the read-modify-write instruction is executed for this register at detecting the STOP con-
______
dition, data may become a value not intended. It is because hardware changes the read/write
bit (RBW) at the above timing.
•I²Ci status register (IICiS1)
Do not execute the read-modify-write instruction for this register because all bits of this register
are changed by hardware.
•I²Ci control register (IICiS1D)
When the read-modify-write instruction is executed for this register at detecting the START
condition or at completing the byte transfer, data may become a value not intended. Because
hardware changes the bit counter (BC0–BC2) at the above timing.
•I²Ci clock control register (IICiS2)
The read-modify-write instruction can be executed for this register.
•I²Ci port selection register (IICiS2D)
Since the read value of high-order 4 bits is indeterminate, the read-modify-write instruction
cannot be used.
•I²Ci transmit buffer register (IICiS0S)
Since the value of all bits is indeterminate, the read-modify-write instruction cannot be used.
Rev.1.00 May 18, 2004 page 144 of 296