M306V7MG_15 Datasheet, PDF (124/300 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER

M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
<UART2>
• Example of transmit timing when transfer data is 8 bits long (parity enabled, one stop bit)
Tc
Transfer clock
Transmit enable
“1”
bit(TE)
“0”
Transmit buffer
“1”
empty flag(TI)
“0”
TxD2
Data is set in UART2 transmit buffer register
Note
Transferred from UART2 transmit buffer register to UARTi transmit register
Start
bit
Parity Stop
bit
bit
ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
Transmit register ^{“1”}
empty flag (TXEPT) _{“0”}
Transmit interrupt ^{“1”}
request bit (IR)
“0”
Shown in ( ) are bit symbols.
Cleared to “0” when interrupt request is accepted, or cleared by software
The above timing applies to the following settings :
• Parity is enabled.
• One stop bit.
• Transmit interrupt cause select bit = “1”.
Tc = 16 (n + 1) / fi
fi : frequency of BRG2 count source (f 1, f8, f32)
n : value set to BRG2
Note: The transmit is started with overflow timing of BRG after having written in a value at the transmit buffer in the above timing.
<UART2, UART0>
• Example of receive timing when transfer data is 8 bits long (parity disabled, one stop bit)
BRGi count
source
“1”
Receive enable bit
“0”
RxDi
Transfer clock
Receive
“1”
complete flag
“0”
RTSi
“H”
“L”
Receive interrupt _{“1”}
request bit
“0”
Start bit
Sampled “L”
D0
D1 D7
Receive data taken in
Stop bit
Reception triggered when transfer clock Transfered from UARTi receive register to
is generated by falling edge of start bit UARTi receive buffer register
Cleared to “0” when interrupt request is accepted, or cleared by software
The above timing applies to the following settings :
•Parity is disabled.
O t bit
Figure 2.11.23 Typical transmit/receive timings in UART mode (2)
Rev.1.00 May 18, 2004 page 122 of 296