HD49334ANP Datasheet, PDF (18/22 Pages) Renesas Technology Corp – CDS/PGA & 10-bit A/D Converter

HD49334ANP/AHNP
Operation Sequence at Power On
V_DD
Start control
of TG and
camera DSP
SPBLK
SPSIG
ADCLK
OBP
etc.
HD49334ANP/AHNP
serial data transfer
RESET bit
Must be stable within the operating
power supply voltage range
0 ms
or more
0 ms
or more
2 ms or more
(1) Register 2 setting
(2) Register 2 setting
0 ms
or more
(3) Registers 0, 1
and 3 settings
2 ms or more
RESET = "Low"
(RESET mode)
RESET = "High"
(RESET cancellation)
Automatic offset
calibration
Offset calibration
(automatically starts
after RESET cancellation)
Ends after 40000 clock cycles
The following describes the above serial data transfer. For details on registers 0, 1, 2, and 3, refer to table 10.
(1) Register 2 setting
: Set all bits in register 2 to the usage condition, and set the RESET bit to low.
(2) Register 2 setting
: Cancel the RESET mode by setting the register 2 RESET bit to high.
Do not change other register 2 settings. Offset calibration starts automatically.
(3) Register 0, 1 and 3 settings : After the offset calibration is terminated, set registers 0, 1 and 3.
Rev.2.00 May 20, 2005 page 18 of 21