HD49334ANP Datasheet, PDF (11/22 Pages) Renesas Technology Corp – CDS/PGA & 10-bit A/D Converter

HD49334ANP/AHNP
Detailed Timing Specifications at Pre-Blanking
Figure 5 shows the pre-blanking detailed timing specifications.
PBLK
Vth
Digital output ADC
(D0 to D9) data
Clamp level
V_OH
ADC
data
t_PBLK
ADCLK × 2 clocks
V_OL
ADCLK × 10 clocks
(shifts one clock cycle depending
on the PBLK input timing)
When serial data SPinv bit is set to low
(When the SPinv is set to high, the PBLK polarity is inverted.)
Figure 5 Detailed Timing Specifications at Pre-Blanking
Detailed Timing Specifications when ADCIN Input Mode is Used
Figure 6 shows the detailed timing chart when ADCIN input mode is used, and table 9 shows each timing specification.
ADCIN
(2)
ADCLK
D0 to D9
(1)
(3)
(4)
(5)
Vth
V_DD/2
Figure 6 Detailed Timing Chart when ADCIN Input Mode is Used
Table 9 Timing Specifications when ADCIN Input Mode is Used
No.
(1)
(2), (3)
(4)
(5)
Timing
Signal fetch time
ADCLK tWH min./tWL min.
ADCLK rising to digital output hold time
ADCLK rising to digital output delay time
Symbol
tADC1
tADC2, 3
tAHLD4
tAOD5
Min
—
Typ × 0.85
10
—
Typ
(6)
1/2fADCLK
14.5
23.5
Max
—
Typ × 1.15
—
31.5
Unit
ns
ns
ns
ns
Rev.2.00 May 20, 2005 page 11 of 21