HD49334ANP Datasheet, PDF (12/22 Pages) Renesas Technology Corp – CDS/PGA & 10-bit A/D Converter

HD49334ANP/AHNP
Serial Interface Specifications
Table 10 Serial Data Function List
Resister 0
Resister 1
DI 00 (LSB)
Low
High
Resister 2
Low
Resister 3
High
Resister 4 to 7 *⁷
Test Mode (can not be used)
Low to High
DI 01
Low
Low
High
High
Low to High
DI 02
DI 03
DI 04
DI 05
DI 06
Low
Cannot be used.
All low
PGA gain setting (LSB)
PGA gain setting
Low
Low
SLP
Low: Normal operation mode
High: Sleep mode
Clamp-level [0] (LSB)
STBY
Low: Normal operation
High: Standby mode
mode
Clamp-level [1]
Output mode setting (LINV) Clamp-level [2]
Output mode setting (MINV) Clamp-level [3]
Low
C-Bias off
Output mode setting (TEST1)
Cannot be used.
All low
High
DI 07
PGA gain setting
Output mode setting (TEST0) Clamp-level [4] (MSB)
0
DI 08
DI 09
PGA gain setting
PGA gain setting
SHA-fsel [0] (LSB)
SHA-fsel [1] (MSB)
SHAMP
frequency
character-
istics
switching
HGstop-Hsel [0]
HGstop-Hsel [1]
High-speed
lead-in
cancellation
time
0
0
DI 10
DI 11
PGA gain setting
PGA gain setting
SHSW-fsel [0] (LSB)
HGain-Nsel [0] ^High-speed 0
lead-in
SHSW
gain
SHSW-fsel [1]
frequency ^{HGain-Nsel [1]} _{multiplication} ⁰
character-
DI 12
PGA gain setting (MSB) SHSW-fsel [2]
istics _{Low_PWR}
1
switching
DI 13
Cannot be used.
SHSW-fsel [3] (MSB)
SPinv,
SPSIG/SPBLK/PBLK inversion
0
DI 14
All low
Cannot be used.
OBPinv, OBP inversion 0
DI 15 (MSB)
CSEL
Low: CDSIN input mode
High: CIN input mode
All low
RESET
Low: Reset mode
High: Normal operation
mode
1
Cannot be used.
Cannot be used.
Latches SDATA
CS
at SCK rising edge
t_INT1
f_SCK
Data is determined
at CS rising edge
t_INT2
SCK
SDATA
t_su
t_ho
DI DI DI DI DI DI DI DI DI DI DI DI DI DI DI DI
00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15
Figure 7 Serial Interface Timing Specifications
Notes: 1. 2 byte continuous communications.
2. SDATA is latched at SCK rising edge.
3. Insert 16 clocks of SCK while CS is low.
4. Data is invalid if data transmission is aborted during transmission.
5. The gain conversion table differs in the CDSIN input mode and the ADCIN input mode.
6. STBY: Reference voltage generator circuit is in the operating state.
SLP: All circuits are in the sleep state.
7. This bit is used for the IC testing, and cannot be used by the user.
The use of this address is prohibited.
8. Circuit current and the frequency characteristic are switched.
Data = 0: 36 MHz guarantee
Data = 1: 25 MHz guarantee
Timing Specifications
f_SCK
t_INT1, 2
t_su
t_ho
Min

50 ns
50 ns
50 ns
Max
5 MHz



Rev.2.00 May 20, 2005 page 12 of 21