R8C2C Datasheet, PDF (157/615 Pages) Renesas Technology Corp – MCU

R8C/2C Group, R8C/2D Group
12. Interrupts
12.1.6.7 Saving a Register
In the interrupt sequence, the FLG register and PC are saved to the stack.
After an extended 16 bits, 4 high-order bits in the PC and 4 high-order (IPL) and 8 low-order bits in the FLG
register, are saved to the stack, the 16 low-order bits in the PC are saved.
Figure 12.8 shows the Stack State Before and After Acknowledgement of Interrupt Request.
The other necessary registers are saved by a program at the beginning of the interrupt routine. The PUSHM
instruction can save several registers in the register bank being currently used⁽¹⁾ with a single instruction.
NOTE:
1. Selectable from registers R0, R1, R2, R3, A0, A1, SB, and FB.
Address
Stack
MSB
LSB
Address
MSB
Stack
LSB
m−4
m−3
m−2
m−1
m
Previous stack contents
m+1 _{Previous stack contents}
[SP]
SP value before
interrupt is generated
m−4
PCL
m−3
PCM
m−2
FLGL
m−1
FLGH
PCH
m
Previous stack contents
m+1 _{Previous stack contents}
[SP]
New SP value
PCH
PCM
PCL
FLGH
FLGL
: 4 high-order bits of PC
: 8 middle-order bits of PC
: 8 low-order bits of PC
: 4 high-order bits of FLG
: 8 low-order bits of FLG
Stack state before interrupt request
is acknowledged
Stack state after interrupt request
is acknowledged
NOTE:
1.When executing software number 32 to 63 INT instructions,
this SP is specified by the U flag. Otherwise it is ISP.
Figure 12.8 Stack State Before and After Acknowledgement of Interrupt Request
The register saving operation, which is performed as part of the interrupt sequence, saved in 8 bits at a time in
four steps.
Figure 12.9 shows the Register Saving Operation.
Figure 12.9
Address
[SP]−5
Stack
Sequence in which
order registers are
saved
[SP]−4
PCL
(3)
[SP]−3
[SP]−2
PCM
FLGL
(4)
Saved, 8 bits at a time
(1)
[SP]−1
[SP]
FLGH
PCH
(2)
Completed saving
registers in four
operations.
PCH
PCM
PCL
FLGH
FLGL
: 4 high-order bits of PC
: 8 middle-order bits of PC
: 8 low-order bits of PC
: 4 high-order bits of FLG
: 8 low-order bits of FLG
NOTE:
1. [SP] indicates the initial value of the SP when an interrupt request is acknowledged.
After registers are saved, the SP content is [SP] minus 4. When executing
software number 32 to 63 INT instructions, this SP is specified by the U
flag. Otherwise it is ISP.
Register Saving Operation
Rev.2.00 Dec 05, 2007 Page 136 of 585
REJ09B0339-0200