AN95089 Datasheet, PDF (14/19 Pages) Ramtron International Corporation – BLE Crystal Oscillator Selection and Tuning Techniques

PSoC® 4/PRoC™ BLE Crystal Oscillator Selection and Tuning Techniques
Figure 12. ppm Variation Across Boards for Same Load Capacitances
ppm variation across boards
80
75
70
65
60
55
50
45
40
35
30
0
2
4
6
8
10
Board#
ppm before tuning
ppm after tuning
The ppm variation across boards with the same load capacitor value is approximately 20 ppm. This is acceptable for
BLE, and therefore, you do not need to tune every board. You can use this approach for mass production, where you
tune 4-5 boards to find out the optimum load capacitance values and then use the same capacitance value for all
theboards during production.
9 Recommendations for WCO
The following factors should be considered while choosing the WCO crystal:
1. ESR: It should be a maximum of 70 kΩ for the correct operation of the crystal circuitry. A higher ESR means a
longer start-up time.
2. Drive Level: The maximum drive level of the crystal should be ≥ 1 µW.
3. ppm variation across the device temperature range: The less the ppm variation, the better it is for power
consumption. Choose a crystal that doesn’t have more than ± 50 ppm variation in frequency at room temperature
after meeting the 2:1 ratio recommendation for load capacitance values.
4. Size: The size of the crystal should be chosen such that it is as small as possible, while meeting three
requirements listed earlier. The ESR of the crystal varies inversely with the crystal size.
Table 4. ESR and Size for WCO Crystals
Part Number
Mfr Drive Level Max ESR
ECS-.327-12.5-34B ECS 1 µW
CM315
Citizen 1 µW
ECS-.327-12.5-32-TR ECS 1 µW
70 kΩ
70 kΩ
50 kΩ
Size (mm)
L×W×H
3.2 × 1.5 × 0.9
3.2 ×1.5 × 0.55
3.2 × 1.2 × 1
10 Layout Considerations for PCB
The crystal frequency is sensitive to parasitic capacitances, board noise, and electromagnetic interference. Keep the
following points in mind while designing a PCB layout:
1 Position the crystal close to the chip to minimize the parasitic capacitance due to longer trace length and wider
trace width, which would consequently alter the load cap value resulting in clock inaccuracy.
2 Minimize the pin-to-pin stray capacitance by having a ground shield trace between pin-connected traces.
3 Place the crystal on the same side of the PCB as the PSoC 4/PRoC BLE chip so that it provides a common
ground plane without unnecessary vias on the crystal input/output traces.
4 Avoid floating pads of conductor near the crystal because this may introduce a stray capacitance.
5 Surround crystal components by a ground fill to avoid electromagnetic interference.
6 Keep fast-switching and high-current traces and pins such as LEDs away from the crystal circuitry.
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Document No. 001-95089 Rev. *A
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