AN95089 Datasheet, PDF (12/19 Pages) Ramtron International Corporation – BLE Crystal Oscillator Selection and Tuning Techniques

PSoC® 4/PRoC™ BLE Crystal Oscillator Selection and Tuning Techniques
The less the variation, the better it is for low-power operations. This is because a larger drift in the low-frequency
clock requires the device in the Peripheral role to listen for a master anchor point over a larger listening time window
at the link layer, thus consuming extra power.
8.2 Start-Up Time and ESR
The startup time indicates how long it takes for the WCO to provide a stable 32.768-kHz clock from the time the block
is enabled.
There are three distinct operating power modes for the WCO:
1. Power-down mode (PDM)
2. High-power mode (HPM)
3. Low-power mode (LPM)
The WCO is started in HPM. After it is stable, it is switched to LPM to conserve power. The startup time with HPM is
500 ms.
After the WCO has switched to LPM, no additional switching of modes is required for the block while the chip is in
active mode or when the chip is switching between active and deep-sleep modes. However, if the chip switches to
the hibernate or stop mode, then the entire WCO startup sequence is initiated again because the chip is reset.
Crystal amplitude in HPM is limited to approximately 1-V pp while in LPM it is limited to approximately 0.12 V pp.
The explained WCO start up sequence is taken care as a part of Creator initialization code and the user does not
have to do this in the application code.
Figure 10. PAD Voltages in Power Modes for WCO
LPM
High Power
Mode
Low Power
Mode
High Power
Mode
0.12V
PAD_xout
1V
1V
PAD_xin
The start-up time is directly related to the ESR of the external crystal. The larger the ESR of the crystal, the longer the
time it takes to start up because the amplification of oscillations during startup takes longer with a larger resistance in
series with the external load capacitors. Because the ESR of the crystal represents this series resistance, longer
start-up times are evident. The crystal ESR characterization shows that the WCO design covers all crystal
manufacturers’ ESR ranges from 35 to 70 kΩ.
8.3 Load Capacitance
Figure 11 shows the external application view of a PSoC 4/PRoC BLE device. Note that no parallel or series resistors
are required externally (they are present on chip). The only external requirements are a 32.768-kHz watch crystal and
two load capacitors, C1 and C2, such that the total effective load capacitance CL is 6 pF or 12.5 pF depending on the
crystal chosen.
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Document No. 001-95089 Rev. *A
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