HYB18TC256800BF Datasheet, PDF (9/62 Pages) Qimonda AG – 256-Mbit Double-Data-Rate-Two SDRAM

Internet Data Sheet
HYB18TC256[80/16]0BF
256-Mbit Double-Data-Rate-Two SDRAM
FIGURE 1
Chip Configuration for ×8 components, PG-TFBGA-60 (top view)









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Notes
1. RDQS / RDQS are enabled by EMRS(1) command.
2. If RDQS / RDQS is enabled, the DM function is disabled
3. When enabled, RDQS & RDQS are used as strobe signals during reads.
4. V_DDL and V_SSDL are power and ground for the DLL. V_DDL is connected to V_DD on the device. V_DD, V_DDQ, V_SSDL, V_SS, and V_SSQ
are isolated on the device.
5. Ball position L8 is A13 for 512-Mbit and is Not Connected on 256-Mbit.
Rev. 1.3, 2007-05
9
07182006-DD60-22E6