HYB18TC256800BF Datasheet, PDF (18/62 Pages) Qimonda AG – 256-Mbit Double-Data-Rate-Two SDRAM

Internet Data Sheet
HYB18TC256[80/16]0BF
256-Mbit Double-Data-Rate-Two SDRAM
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Field Bits
Type¹⁾
TABLE 16
EMRS(2) Programming Extended Mode Register Definition (BA[2:0]=010_B)
Description
BA [15:14] w
Bank Adress
00_B BA MRS
01_B BA EMRS(1)
10_B BA EMRS(2)
11_B BA EMRS(3): Reserved
SRF 7
w
Address Bus, High Temperature Self Refresh Rate for T_CASE > 85°C
0_B A7 disable
1_B A7 enable ²⁾
A
[6:4] w
Address Bus
000_B A Address bits
DCC 3
w
Address Bus, Duty Cycle Correction (DCC)
0_B A3 DCC disabled
1_B A3 DCC enabled
Partial Self Refresh for 4 banks
PASR [2:0] w
Address Bus, Partial Array Self Refresh for 4 Banks³⁾
Note: Only for 256 Mbit and 512 Mbit components
000_B PASR0 Full Array
001_B PASR1 Half Array (BA[1:0]=00, 01)
010_B PASR2 Quarter Array (BA[1:0]=00)
011_B PASR3 Not defined
100_B PASR4 3/4 array (BA[1:0]=01, 10, 11)
101_B PASR5 Half array (BA[1:0]=10, 11)
110_B PASR6 Quarter array (BA[1:0]=11)
111_B PASR7 Not defined
1) w = write only
2) When DRAM is operated at 85 °C ≤ T_Case ≤ 95 °C the extended self refresh rate must be enabled by setting bit A7 to "1" before the self
refresh mode can be entered.
3) If PASR (Partial Array Self Refresh) is enabled, data located in areas of the array beyond the specified location will be lost if self refresh
is entered. Data integrity will be maintained if t_REF conditions are met and no Self Refresh command is issued
Rev. 1.3, 2007-05
18
07182006-DD60-22E6