HYB18TC256800BF Datasheet, PDF (6/62 Pages) Qimonda AG – 256-Mbit Double-Data-Rate-Two SDRAM

Internet Data Sheet
HYB18TC256[80/16]0BF
256-Mbit Double-Data-Rate-Two SDRAM
2
Configuration
This chapter contains the chip configuration, addressing.
2.1
Chip Configuration for PG-TFBGA-60
The chip configuration of a DDR2 SDRAM is listed by function in Table 6. The abbreviations used in the Ball# columns are
explained in Table 7 and Table 8 respectively. The ball numbering for the FBGA package is depicted in figures.
Ball#
Name
Ball
Type
Clock Signals ×8 organization
E8
CK
I
F8
CK
I
F2
CKE
I
Control Signals ×8 organizations
F7
RAS
I
G7
CAS
I
F3
WE
I
G8
CS
I
Address Signals ×8 organizations
G2
BA0
I
G3
BA1
I
H8
A0
I
H3
A1
I
H7
A2
I
J2
A3
I
J8
A4
I
J3
A5
I
J7
A6
I
K2
A7
I
K8
A8
I
K3
A9
I
H2
A10
I
AP
I
K7
A11
I
L2
A12
I
Buffer
Type
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
Function
TABLE 6
Chip Configuration of DDR2 SDRAM
Clock Signal CK, CK
Clock Enable
Row Address Strobe (RAS), Column Address Strobe (CAS), Write
Enable (WE)
Chip Select
Bank Address Bus 1:0
Address Signal 12:0, Address Signal 10/Autoprecharge
Rev. 1.3, 2007-05
6
07182006-DD60-22E6