HYB18TC256800BF Datasheet, PDF(13/62 Page) Qimonda AG – 256-Mbit Double-Data-Rate-Two SDRAM

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HYB18TC256800BF Datasheet, PDF (13/62 Pages) Qimonda AG – 256-Mbit Double-Data-Rate-Two SDRAM

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Internet Data Sheet

HYB18TC256[80/16]0BF

256-Mbit Double-Data-Rate-Two SDRAM

FIGURE 2

Ball Configuration for Ã16 components, PG-TFBGA-84 (top view)

6''

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03 37

Notes

1. UDQS/UDQS is data strobe for DQ[15:8], LDQS/LDQS is data strobe for DQ[7:0]

2. LDM is the data mask signal for DQ[7:0], UDM is the data mask signal for DQ[15:8]

3. VDDL and VSSDL are power and ground for the DLL. VDDL is connected to VDD on the device. VDD, VDDQ, VSSDL, VSS, and VSSQ

are isolated on the device.

Rev. 1.3, 2007-05

13

07182006-DD60-22E6

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