HYS64T32X00EDL Datasheet, PDF (6/86 Pages) Qimonda AG – 200-Pin SO-DIMM DDR2 SDRAM Modules

Internet Data Sheet
HYS64T[32/64/128]xxxEDL–[25F/…/3.7](–)B2
Small Outlined DDR2 SDRAM Modules
2
Pin Configurations
2.1
Chip Configuration
The chip configuration of the Small Outline DDR2 SDRAM DIMM is listed by function in Table 2 (200 balls). The abbreviations
used in columns Ball and Buffer Type are explained in Table 3 and Table 4 respectively. The Ball numbering is depicted in
Figure 1.
Ball No.
Clock Signals
30
164
32
166
79
80
Control Signals
110
115
108
113
109
Address Signals
107
106
85
Name Pin Buffer Function
Type Type
TABLE 5
Chip Configuration of SO-DIMM
CK0
I
CK1
I
CK0
I
CK1
I
CKE0 I
CKE1 I
NC
NC
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
—
Clock Signals 2:0, Complement Clock Signals 2:0
Clock Enable Rank 1:0
Note: 2 Ranks module
Not Connected
Note: 1-rank module
S0
S1
NC
RAS
CAS
WE
I
SSTL Chip Select Rank 1:0
I
SSTL
NC —
Not Connected
Note: 1-rank module
I
SSTL Row Address Strobe
I
SSTL Column Address Strobe
I
SSTL Write Enable
BA0
I
SSTL Bank Address Bus 2:0
BA1
I
SSTL
BA2
I
SSTL Bank Address Bus 2
Greater than 512Mb DDR2 SDRAMS
NC
NC SSTL Less than 1Gb DDR2 SDRAMS
Rev. 1.1, 2007-01
6
08212006-PKYN-2H1B