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HYS64T32X00EDL Datasheet, PDF (28/86 Pages) Qimonda AG – 200-Pin SO-DIMM DDR2 SDRAM Modules | |||
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Internet Data Sheet
HYS64T[32/64/128]xxxEDLâ[25F/â¦/3.7](â)B2
Small Outlined DDR2 SDRAM Modules
3.4
IDD Specifications and Conditions
List of tables defining IDD Specifications and Conditions.
⢠Table 20 âIDD Measurement Conditionsâ on Page 28
⢠Table 21 âDefinitions for IDDâ on Page 29
⢠Table 22 âIDD Specification for HYS64T[32/64/128]xxxEDLâ25FâB2â on Page 30
⢠Table 23 âIDD Specification for HYS64T[32/64/128]xxxEDLâ2.5âB2â on Page 31
⢠Table 24 âIDD Specification for HYS64T[32/64/128]xxxEDLâ3âB2â on Page 32
⢠Table 25 âIDD Specification for HYS64T[32/64/128]xxxEDLâ3SâB2â on Page 33
⢠Table 26 âIDD Specification for HYS64T[32/64/128]xxxEDLâ3.7âB2â on Page 34
Parameter
TABLE 20
IDD Measurement Conditions
Symbol Note
1)2)3)4)5)
Operating Current 0
IDD0
â
One bank Active - Precharge; tCK = tCK.MIN, tRC = tRC.MIN, tRAS = tRAS.MIN, CKE is HIGH, CS is HIGH between
valid commands. Address and control inputs are SWITCHING, Databus inputs are SWITCHING.
Operating Current 1
IDD1
6)
One bank Active - Read - Precharge; IOUT = 0 mA, BL = 4, tCK = tCK.MIN, tRC = tRC.MIN, tRAS = tRAS.MIN,
tRCD = tRCD.MIN, AL = 0, CL = CLMIN; CKE is HIGH, CS is HIGH between valid commands. Address and
control inputs are SWITCHING, Databus inputs are SWITCHING.
Precharge Standby Current
IDD2N
â
All banks idle; CS is HIGH; CKE is HIGH; tCK = tCK.MIN; Other control and address inputs are SWITCHING,
Databus inputs are SWITCHING.
Precharge Power-Down Current
Other control and address inputs are STABLE, Data bus inputs are FLOATING.
IDD2P
â
Precharge Quiet Standby Current
IDD2Q
â
All banks idle; CS is HIGH; CKE is HIGH; tCK = tCK.MIN; Other control and address inputs are STABLE,
Data bus inputs are FLOATING.
Active Standby Current
IDD3N
â
Burst Read: All banks open; Continuous burst reads; BL = 4; AL = 0, CL = CLMIN; tCK = tCK.MIN;
tRAS = tRAS.MAX, tRP = tRP.MIN; CKE is HIGH, CS is HIGH between valid commands. Address inputs are
SWITCHING; Data Bus inputs are SWITCHING; IOUT = 0 mA.
Active Power-Down Current
IDD3P(0) â
All banks open; tCK = tCK.MIN, CKE is LOW; Other control and address inputs are STABLE, Data bus inputs
are FLOATING. MRS A12 bit is set to LOW (Fast Power-down Exit);
Active Power-Down Current
IDD3P(1) â
All banks open; tCK = tCK.MIN, CKE is LOW; Other control and address inputs are STABLE, Data bus inputs
are FLOATING. MRS A12 bit is set to HIGH (Slow Power-down Exit);
Operating Current - Burst Read
IDD4R
6)
All banks open; Continuous burst reads; BL = 4; AL = 0, CL = CLMIN; tCK = tCKMIN; tRAS = tRASMAX;
tRP = tRPMIN; CKE is HIGH, CS is HIGH between valid commands; Address inputs are SWITCHING; Data
bus inputs are SWITCHING; IOUT = 0mA.
Operating Current - Burst Write
IDD4W
â
All banks open; Continuous burst writes; BL = 4; AL = 0, CL = CLMIN; tCK = tCK.MIN;
tRAS = tRAS.MAX., tRP = tRP.MAX; CKE is HIGH, CS is HIGH between valid commands. Address inputs are
SWITCHING; Data Bus inputs are SWITCHING;
Rev. 1.1, 2007-01
28
08212006-PKYN-2H1B
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