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HYS64T256020EU-25F-B Datasheet, PDF (52/60 Pages) Qimonda AG – 240-Pin unbuffered DDR2 SDRAM Modules | |||
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Internet Data Sheet
HYS[64/72]T256020EU-[25F/2.5/3/3S/3.7]-B
Unbuffered DDR2 SDRAM Module
Product Type
Organization
Label Code
JEDEC SPD Revision
Byte#
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
Description
tRAS.MIN [ns]
Module Density per Rank
tAS.MIN and tCS.MIN [ns]
tAH.MIN and tCH.MIN [ns]
tDS.MIN [ns]
tDH.MIN [ns]
tWR.MIN [ns]
tWTR.MIN [ns]
tRTP.MIN [ns]
Analysis Characteristics
tRC and tRFC Extension
tRC.MIN [ns]
tRFC.MIN [ns]
tCK.MAX [ns]
tDQSQ.MAX [ns]
tQHS.MAX [ns]
PLL Relock Time
TCASE.MAX Delta / âT4R4W Delta
Psi(T-A) DRAM
âT0 (DT0)
âT2N (DT2N, UDIMM) or âT2Q (DT2Q, RDIMM)
âT2P (DT2P)
âT3N (DT3N)
âT3P.fast (DT3P fast)
âT3P.slow (DT3P slow)
âT4R (DT4R) / âT4R4W Sign (DT4R4W)
âT5B (DT5B)
âT7 (DT7)
Psi(ca) PLL
Psi(ca) REG
âTPLL (DTPLL)
âTREG (DTREG) / Toggle Rate
SPD Revision
HYS64T256020EUâ3.7âB HYS72T256020EUâ3.7âB
2 GByte
2 GByte
Ã64
Ã72
2 Ranks (Ã8)
2 Ranks (Ã8)
PC2â4200Uâ444
PC2â4200Eâ444
Rev. 1.2
Rev. 1.2
HEX
2D
01
25
37
10
22
3C
1E
1E
00
06
3C
7F
80
1E
28
00
52
60
37
2A
2B
20
35
21
36
22
25
00
00
00
00
12
HEX
2D
01
25
37
10
22
3C
1E
1E
00
06
3C
7F
80
1E
28
00
52
60
37
2A
2B
20
35
21
36
22
25
00
00
00
00
12
Rev. 1.0, 2006-10
52
10262006-SX8C-DEY8
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