HYS64T256020EU-25F-B Datasheet, PDF (40/60 Pages) Qimonda AG – 240-Pin unbuffered DDR2 SDRAM Modules

Internet Data Sheet
HYS[64/72]T256020EU-[25F/2.5/3/3S/3.7]-B
Unbuffered DDR2 SDRAM Module
Product Type
Organization
Label Code
JEDEC SPD Revision
Byte#
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
Description
t_RAS.MIN [ns]
Module Density per Rank
t_AS.MIN and t_CS.MIN [ns]
t_AH.MIN and t_CH.MIN [ns]
t_DS.MIN [ns]
t_DH.MIN [ns]
t_WR.MIN [ns]
t_WTR.MIN [ns]
t_RTP.MIN [ns]
Analysis Characteristics
t_RC and t_RFC Extension
t_RC.MIN [ns]
t_RFC.MIN [ns]
t_CK.MAX [ns]
t_DQSQ.MAX [ns]
t_QHS.MAX [ns]
PLL Relock Time
T_CASE.MAX Delta / ∆T_4R4W Delta
Psi(T-A) DRAM
∆T₀ (DT0)
∆T_2N (DT2N, UDIMM) or ∆T_2Q (DT2Q, RDIMM)
∆T_2P (DT2P)
∆T_3N (DT3N)
∆T_3P.fast (DT3P fast)
∆T_3P.slow (DT3P slow)
∆T_4R (DT4R) / ∆T_4R4W Sign (DT4R4W)
∆T_5B (DT5B)
∆T₇ (DT7)
Psi(ca) PLL
Psi(ca) REG
∆T_PLL (DTPLL)
∆T_REG (DTREG) / Toggle Rate
SPD Revision
HYS64T256020EU–2.5–B HYS72T256020EU–2.5–B
2 GByte
2 GByte
×64
×72
2 Ranks (×8)
2 Ranks (×8)
PC2–6400U–666
PC2–6400E–666
Rev. 1.2
Rev. 1.2
HEX
2D
01
17
25
05
12
3C
1E
1E
00
06
3C
7F
80
14
1E
00
57
60
57
40
2B
2E
49
21
4E
25
36
00
00
00
00
12
HEX
2D
01
17
25
05
12
3C
1E
1E
00
06
3C
7F
80
14
1E
00
57
60
57
40
2B
2E
49
21
4E
25
36
00
00
00
00
12
Rev. 1.0, 2006-10
40
10262006-SX8C-DEY8