HYS72T256000ER Datasheet, PDF (26/33 Pages) Qimonda AG – 240-Pin Registered DDR2 SDRAM Modules

Internet Data Sheet
HYS72T256000ER-[3.7/5]-B
Registerd DDR2 SDRAM Module
Product Type
Organization
Label Code
JEDEC SPD Revision
Byte#
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
Description
Component Attributes
t_CK @ CL_MAX -1 (Byte 18) [ns]
t_AC SDRAM @ CL_MAX -1 [ns]
t_CK @ CL_MAX -2 (Byte 18) [ns]
t_AC SDRAM @ CL_MAX -2 [ns]
t_RP.MIN [ns]
t_RRD.MIN [ns]
t_RCD.MIN [ns]
t_RAS.MIN [ns]
Module Density per Rank
t_AS.MIN and t_CS.MIN [ns]
t_AH.MIN and t_CH.MIN [ns]
t_DS.MIN [ns]
t_DH.MIN [ns]
t_WR.MIN [ns]
t_WTR.MIN [ns]
t_RTP.MIN [ns]
Analysis Characteristics
t_RC and t_RFC Extension
t_RC.MIN [ns]
t_RFC.MIN [ns]
t_CK.MAX [ns]
t_DQSQ.MAX [ns]
t_QHS.MAX [ns]
PLL Relock Time
T_CASE.MAX Delta / ∆T_4R4W Delta
Psi(T-A) DRAM
∆T₀ (DT0)
∆T_2N (DT2N, UDIMM) or ∆T_2Q (DT2Q, RDIMM)
∆T_2P (DT2P)
∆T_3N (DT3N)
∆T_3P.fast (DT3P fast)
∆T_3P.slow (DT3P slow)
HYS72T256000ER–3.7–B HYS72T256000ER–5–B
2 GByte
2 GByte
×72
×72
1 Rank (×4)
1 Rank (×4)
PC2–4200R–444
PC2–3200R–333
Rev. 1.2
Rev. 1.2
HEX
07
3D
50
50
60
3C
1E
3C
2D
02
25
37
10
22
3C
1E
1E
00
06
3C
7F
80
1E
28
0F
52
60
37
20
2B
20
35
21
HEX
07
50
60
50
60
3C
1E
3C
28
02
35
47
15
27
3C
28
1E
00
06
37
7F
80
23
2D
0F
51
60
33
1D
2B
1C
2C
21
Rev. 1.0, 2006-10
26
10202006-EHWJ-OT02