HYS72T256000ER Datasheet, PDF (15/33 Pages) Qimonda AG – 240-Pin Registered DDR2 SDRAM Modules

Internet Data Sheet
HYS72T256000ER-[3.7/5]-B
Registerd DDR2 SDRAM Module
3.3
Timing Characteristics
This chapter describes the timing characteristics.
3.3.1
Speed Grade Definitions
All Speed grades faster than DDR2-400B comply with DDR2-400B timing specifications(t_CK = 5ns with t_RAS = 40ns).
Speed Grade Definitions: Table 12 for DDR2–533C and Table 13 for DDR2–400B
Speed Grade
TABLE 12
Speed Grade Definition Speed Bins for DDR2–533C
DDR2–533C
Unit
Note
QAG Sort Name
–3.7
CAS-RCD-RP latencies
4–4–4
t_CK
Parameter
Symbol
Min.
Max.
—
Clock Frequency
@ CL = 3
t_CK
5
8
ns
1)2)3)4)
@ CL = 4
t_CK
3.75
8
ns
1)2)3)4)
@ CL = 5
t_CK
3.75
8
ns
1)2)3)4)
Row Active Time
t_RAS
45
70000
ns
1)2)3)4)5)
Row Cycle Time
t_RC
60
—
ns
1)2)3)4)
RAS-CAS-Delay
t_RCD
15
—
ns
1)2)3)4)
Row Precharge Time
t_RP
15
—
ns
1)2)3)4)
1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew
Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. Timings are further guaranteed for normal
OCD drive strength (EMRS(1) A1 = 0)
2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS,
input reference level is the crosspoint when in differential strobe mode.
3) Inputs are not recognized as valid until V_REF stabilizes. During the period before V_REF stabilizes, CKE = 0.2 x V_DDQ is recognized as low.
4) The output timing reference voltage level is V_TT.
5) t_RAS.MAX is calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is equal to 9 x t_REFI.
Speed Grade
QAG Sort Name
CAS-RCD-RP latencies
Parameter
Clock Frequency
Row Active Time
@ CL = 3
@ CL = 4
@ CL = 5
Rev. 1.0, 2006-10
10202006-EHWJ-OT02
TABLE 13
Speed Grade Definition Speed Bins for DDR2-400B
DDR2–400B
Unit
Note
–5
Symbol
t_CK
t_CK
t_CK
t_RAS
3–3–3
Min.
5
5
5
40
Max.
8
8
8
70000
t_CK
—
ns
1)2)3)4)
ns
1)2)3)4)
ns
1)2)3)4)
ns
1)2)3)4)5)
15