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HYS72T256000ER Datasheet, PDF (17/33 Pages) Qimonda AG – 240-Pin Registered DDR2 SDRAM Modules
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Internet Data Sheet
HYS72T256000ER-[3.7/5]-B
Registerd DDR2 SDRAM Module
Parameter
Symbol
DQ and DM input setup time (differential data tDS(base)
strobe)
DQ and DM input setup time (single ended data tDS1(base)
strobe)
DQS falling edge hold time from CK (write
tDSH
cycle)
DQS falling edge to CK setup time (write cycle) tDSS
Four Activate Window period
tFAW
Clock half period
Data-out high-impedance time from CK / CK
Address and control input hold time
Address and control input pulse width
(each input)
Address and control input setup time
DQ low-impedance time from CK / CK
DQS low-impedance from CK / CK
Mode register set command cycle time
OCD drive mode output delay
Data output hold time from DQS
Data hold skew factor
Average periodic refresh Interval
tHP
tHZ
tIH(base)
tIPW
tIS(base)
tLZ(DQ)
tLZ(DQS)
tMRD
tOIT
tQH
tQHS
tREFI
Auto-Refresh to Active/Auto-Refresh
command period
Precharge-All (4 banks) command period
Precharge-All (8 banks) command period
Read preamble
Read postamble
Active bank A to Active bank B command
period
Internal Read to Precharge command delay
Write preamble
Write postamble
Write recovery time for write without Auto-
Precharge
Write recovery time for write with Auto-
Precharge
Internal Write to Read command delay
Exit power down to any valid command
(other than NOP or Deselect)
tRFC
tRP
tRP
tRPRE
tRPST
tRRD
tRTP
tWPRE
tWPST
tWR
WR
tWTR
tXARD
DDR2–533
Min.
100
–25
0.2
0.2
37.5
50
MIN. (tCL, tCH)
—
375
0.6
250
2 × tAC.MIN
tAC.MIN
2
0
tHP –tQHS
—
—
—
127.5
tRP + 1tCK
15 + 1tCK
0.9
0.40
7.5
10
7.5
0.25 x tCK
0.40
15
tWR/tCK
7.5
2
Max.
—
—
—
—
—
—
tAC.MAX
—
—
—
tAC.MAX
tAC.MAX
—
12
—
400
7.8
3.9
—
—
—
1.1
0.60
—
—
—
—
0.60
—
—
—
—
Unit
Note1)2)3)4)5)
6)7)
ps
11)
ps
11)
tCK
tCK
ns
ns
13)
—
12)
ps
13)
ps
11)
tCK
ps
11)
ps
14)
ps
14)
tCK
ns
—
ps
µs
14)15)
µs
16)18)
ns
17)
ns
ns
tCK
14)
tCK
14)
ns
14)18)
ns
16)20)
ns
tCK
tCK
19)
ns
tCK
20)
ns
21)
tCK
22)
Rev. 1.0, 2006-10
17
10202006-EHWJ-OT02
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