HYS72T512020HR Datasheet, PDF (24/37 Pages) Qimonda AG – 240-Pin Registered-DDR2-SDRAM Modules

Internet Data Sheet
HYS72T512020HR–[3.7/5]–A
Registered DDR2 SDRAM Modules
3.4.1
Currents Test Conditions
For testing the I_DD parameters, the following timing parameters are used:
Parameter
TABLE 18
I_DD Measurement Test Conditions for DDR2–400 and DDR2–533
Symbol
–3.7
–5
Unit
CAS Latency
Clock Cycle Time
Active to Read or Write delay
Active to Active / Auto-Refresh command period
Active bank A to Active bank B command delay
Active to Precharge Command
Precharge Command Period
Auto-Refresh to Active / Auto-Refresh command period
Average periodic Refresh interval
DDR2–533C
DDR2–400B
CL_(IDD)
4
3
t_CK
t_CK(IDD)
3.75
5
ns
t_RCD(IDD)
15
15
ns
t_RC(IDD)
60
55
ns
t_RAS.MIN(IDD)
45
40
ns
t_RAS.MAX(IDD) 70000
70000
ns
t_RP(IDD)
15
15
ns
t_RFC(IDD)
127.5
127.5
ns
t_REFI
7.8
7.8
µs
3.4.2
On Die Termination (ODT) Current
The ODT function adds additional current consumption to the
DDR2 SDRAM when enabled by the EMRS(1). Depending on
address bits A[6,2] in the EMRS(1) a “weak” or “strong”
termination can be selected. The current consumption for any
terminated input pin, depends on the input pin is in tri-state or
driving 0 or 1, as long a ODT is enabled during a given period
of time.
Parameter
Symbol Min.
Enabled ODT current per DQODT is HIGH; Data I_ODTO
5
Bus inputs are FLOATING
2.5
Active ODT current per DQODT is HIGH; worst I_ODTT
10
case of Data Bus inputs are STABLE or
5
SWITCHING.
Typ.
6
3
12
6
TABLE 19
ODT current per terminated pin
Max. Unit
EMRS(1) State
7.5
mA/DQ A6 = 0, A2 = 1
3.75 mA/DQ A6 = 1, A2 = 0
15
mA/DQ A6 = 0, A2 = 1
7.5
mA/DQ A6 = 1, A2 = 0
Rev. 1.11, 2006-09
26
03062006-TZ8J-GNDA