HYS72T512020HR Datasheet, PDF (16/37 Pages) Qimonda AG – 240-Pin Registered-DDR2-SDRAM Modules

Internet Data Sheet
HYS72T512020HR–[3.7/5]–A
Registered DDR2 SDRAM Modules
3.3.2
AC Timing Parameters
This chapter contains the AC Timing Parameters.
Parameter
Symbol
TABLE 12
Timing Parameter by Speed Grade - DDR2-400 & DDR2-533
DDR2–533
Min.
Max.
DDR2–400
Min.
Max.
Unit Note¹⁾²⁾
3)4)5)6)7)
DQ output access time from CK/CK t_AC
CAS A to CAS B command period t_CCD
CK,CK high-level width
t_CH
CKE minimum high and low pulse
t_CKE
width
CK,CK low-level width
t_CL
Auto-Precharge write recovery +
t_DAL
precharge time
Minimum time clocks remain ON after t_DELAY
CKE asynchronously drops LOW
DQ and DM input hold time
(differential data strobe)
t_DH(base)
DQ and DM input hold time (single
ended data strobe)
t_DH1(base)
DQ and DM input pulse width (each t_DIPW
input)
DQS output access time from CK/CK
DQS input low (high) pulse width
(write cycle)
t_DQSCK
t_DQSL,H
DQS-DQ skew (for DQS & associated t_DQSQ
DQ signals)
Write command to 1st DQS latching t_DQSS
transition
DQ and DM input setup time
(differential data strobe)
t_DS(base)
DQ and DM input setup time (single t_DS1(base)
ended data strobe)
DQS falling edge hold time from CK t_DSH
(write cycle)
DQS falling edge to CK setup time t_DSS
(write cycle)
Four Activate Window period
t_FAW
Clock half period
Data-out high-impedance time from
CK/CK
Address and control input hold time
t_HP
t_HZ
t_IH(base)
–500
2
0.45
3
+500
—
0.55
—
0.45
WR + t_RP
0.55
—
t_IS + t_CK + t_IH ––
225
––
–25
—
0.35
—
–450
0.35
+450
—
—
300
– 0.25
+ 0.25
100
—
–25
—
0.2
—
0.2
—
37.5
—
50
—
MIN. (t_CL, t_CH)
—
t_AC.MAX
375
—
–600
2
0.45
3
+600
—
0.55
—
0.45
WR + t_RP
0.55
—
t_IS + t_CK + t_IH —
275
––
25
—
0.35
—
–500
0.35
+500
—
—
350
– 0.25
+ 0.25
150
—
25
—
0.2
—
0.2
—
37.5
—
50
—
MIN. (t_CL, t_CH)
—
t_AC.MAX
475
—
ps
t_CK
t_CK
t_CK
t_CK
t_CK
ns
ps
ps
t_CK
ps
t_CK
ps
t_CK
ps
ps
t_CK
t_CK
ns
ns ⁸⁾
ps
ps
Rev. 1.11, 2006-09
18
03062006-TZ8J-GNDA