HYS72T512020HR Datasheet, PDF (18/37 Pages) Qimonda AG – 240-Pin Registered-DDR2-SDRAM Modules

Internet Data Sheet
HYS72T512020HR–[3.7/5]–A
Registered DDR2 SDRAM Modules
3) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down
and then restarted through the specified initialization sequence before normal operation can continue.
4) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew
Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode.
5) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS/DQS, RDQS/RDQS,
input reference level is the crosspoint when in differential strobe mode
6) Inputs are not recognized as valid until V_REF stabilizes. During the period before V_REF stabilizes, CKE = 0.2 x V_DDQ is recognized as low.
7) The output timing reference voltage level is V_TT.
8) x16 (2k page size), not on 256 Mbit component
9) 0 ≤ T_CASE ≤ 85 °C
10) 85 °C < T_CASE ≤ 95 °C
11) x4 & x8
Rev. 1.11, 2006-09
20
03062006-TZ8J-GNDA