PACE1750AE Datasheet, PDF (6/25 Pages) Pyramid Semiconductor Corporation – SINGLE CHIP, 20MHz to 40MHz, ENHANCED CMOS 16-BIT PROCESSOR

PACE1750AE
SIGNAL PROPAGATION DELAYS^1,2 (continued)
Symbol
Parameter
t_FC(IBD)V ^IB0^-IB15
t_C(SNW) ^SNEW
t_FC(TGO) ^{TRIGO RST}
t_{RSTL(DMA ENL)} ^{DMA enable}
t_C(DME) ^{DMA enable}
t_FC(NPU) ^{Normal power up}
t_C(ER)
Clock to major error unrecoverable
t_RSTL(NPU) ^RESET
t_REQV(C) ^{Console request}
t_C(REQ)X ^{Console request}
t_FV(BB)H ^{Level sensitive faults}
t_BBH(F)X ^{Level sensitive faults}
t_IRV(C)
IOL_1-2INT user interrupt (0-5) setup
t_C(IR)X
Power down interrupt level sensitive
hold
t_RSTL (t_RSTH) ^{Reset pulse width}
t_C(XX)Z ^{Clock to three-state}
t_f(F), t₁₍₁₎ ^{Edge sensitiive pulse width}
t_r, t_f
Clock rise and fall
20 MHz
Min
Max
25
26
26
35
35
35
50
40
0
10
5
5
0
10
20
17
5
5
30 MHz
Min
Max
25
25
25
35
35
35
50
40
0
10
5
5
0
10
20
17
5
5
40 MHz
Min
Max Unit
20 ns
22 ns
22 ns
30 ns
30 ns
30 ns
45 ns
30 ns
0
ns
10
ns
5
ns
5
ns
0
ns
10
ns
15
ns
13 ns
5
ns
5
ns
Notes
1. 4.5V ≤ V_CC ≤ 5.5V, –55°C ≤ T_C ≤ +125°C. Unless otherwise specified, testing shall be conducted at worst-case conditions.
2. All timing parameters are composed of Three elements. The first "t" stands for timing. The second represents the "from" signal. The third in
parentheses indicates "to" signal. When the CPU clock is one of the signal elements, either the rising edge "C" or the falling edge "FC" is referenced.
When other elements are used, an additional suffix indicates the final logic level of the signal. "L" - low level, "H" - high level, "V" - valid, "Z" - high
impedance, "X" - don't care, "LH" - low to high, "ZH" - high impedance to high, "R" - read cycle, and "W" - write cycle.
Document # MICRO-2 REV G
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