PACE1750AE Datasheet, PDF (5/25 Pages) Pyramid Semiconductor Corporation – SINGLE CHIP, 20MHz to 40MHz, ENHANCED CMOS 16-BIT PROCESSOR

SIGNAL PROPAGATION DELAYS^1,2
Symbol
Parameter
t_C(BR)L ^{BUS REQ}
t_C(BR)H ^{BUS REQ}
t_BGV(C) ^{BUS GNT setup}
t_C(BG)X ^{BUS GNT hold}
t_C(BB)L ^{BUS BUSY LOW}
t_C(BB)H ^{BUS BUSY HIGH}
t_BBV(C) ^{BUS BUSY setup}
t_C(BB)X ^{BUS BUSY hold}
t_C(BL)L ^{BUS LOCK LOW}
t_C(BL)H ^{BUS LOCK HIGH}
t_BLV(C) ^{BUS LOCK setup}
t_{C(BL)X (IN)} ^{BUS LOCK hold}
t_{C(ST )V}
D/I Status, AS₀-AS₃, AK₀-AK₃,
M/IO, R/W
t_{C(ST )X}
M/IO, R/W, D/I Status,
AS₀-AS₃, AK₀-AK₃
t_C(SA)H ^{STRBA HIGH}
t_C(SA)L ^{STRBA LOW}
t_SAL(IBA)X ^{Address hold from STRBA LOW}
t_RAV(C) ^{RDYA setup}
t_C(RA)X ^{RDYA hold}
t_C(SDW)L ^{STRBD LOW write}
t_C(SD)H ^{STRBD HIGH}
t_FC(SDR)L ^{STRBD LOW read}
t_SDRH(IBD)X ^{STRBD HIGH}
t_SDWH(IBD)X ^{STRBD HIGH}
t_SDL(SD)H ^{STRBD write}
t_RDV(C) ^{RDYD setup}
t_C(RD)X ^{RDYD hold}
t_C(IBA)V ^IB0^-IB15
t_FC(IBA)X ^IB0^-IB15
t_IBDRV(C) ^IB0^-IB15 ^setup
t_C(IBD)X ^IB0^-IB15 ^{hold (read)}
t_C(IBD)X ^{Data valid out (write)}
20 MHz
Min
Max
25
25
5
5
24
20
5
5
25
20
5
5
20
25
0
17
17
5
5
5
17
17
17
0
25
26
5
5
25
0
5
6
0
30 MHz
Min
Max
25
25
5
5
24
20
5
5
25
20
5
5
20
25
0
17
17
5
5
5
17
17
17
0
25
26
5
5
25
0
5
6
0
PACE1750AE
40 MHz
Min
Max Unit
22 ns
22 ns
5
ns
5
ns
20 ns
15 ns
5
ns
5
ns
21 ns
17 ns
5
ns
5
ns
20 ns
20 ns
0
ns
16 ns
16 ns
5
ns
5
ns
5
ns
14 ns
14 ns
14 ns
0
ns
17
ns
20
ns
5
ns
5
ns
20 ns
0
ns
5
ns
5
ns
0
ns
Document # MICRO-2 REV G
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