PACE1750AE Datasheet, PDF (14/25 Pages) Pyramid Semiconductor Corporation – SINGLE CHIP, 20MHz to 40MHz, ENHANCED CMOS 16-BIT PROCESSOR

PACE1750AE
SIGNAL DESCRIPTIONS (Continued)
BUS CONTROL
Mnemonic
Name
Description
D/I
Data or instruction
An output signal that indicates whether the current bus cycle access is for
Data (HIGH) or Instruction (LOW). It is three-state during bus cycles not
assigned to the CPU. This line can be used as an additional memory
address bit for systems that require separate data and program memory.
R/W
Read or write
An output signal that indicates direction of data flow with respect to the
current bus master. A HIGH indicates a read or input operation and a
LOW indicates a write or output operation. The signal is three-state during
bus cycles not assigned to the CPU.
M/IO
Memory or I/O
An output signal that indicates whether the current bus cycle is memory
(HIGH) or I/O (LOW). This signal is three-state during bus cycles not
assigned to the CPU.
STRBA
Address strobe
An active HIGH output that can be used to externally latch the memory or
I/O address at the HIGH-to-LOW transition of the strobe. The signal is
three-state during bus cycles not assigned to the CPU.
RDYA
Address ready
An active HIGH input that can be used to extend the address phase of a
bus cycle. When RDYA is not active, wait states are inserted by the device
to accommodate slower memory or I/O devices.
STRBD
Data strobe
An active LOW output that can be used to strobe data in memory and XIO
cycles. This signal is three-state during bus cycles not assigned to the
CPU.
RDYD
Data ready
An active HIGH input that extends the data phase of a bus cycle. When
RDYD is not active, wait states are inserted by the device to accommodate
slower memory or I/O devlces.
INFORMATION BUS
Mnemonic
Name
IB₀ - IB₁₅
Information bus
STATUS BUS
Mnemonic
AK₀ - AK₃
Name
Access key
AS₀ - AS₃
Address state
Description
A bidirectional time-multiplexed address/data bus that is three-state
during bus cycles not assigned to the CPU. IB₀ is the most significant bit.
Description
Outputs used to match the access lock in the MMU for memory accesses
(a mismatch will cause the MMU to pull the MEM PRT ER signal LOW),
and also indicates processor state (PS). Privileged instructions can be
executed with PS = 0 only. These signals are three-state during bus
cycles not assigned to the CPU.
Outputs that select the page register group in the MMU. It is three-state
during bus cycles not assigned to the CPU. These outputs together with
D/I can be used to expand the device direct addressing space to 4
MBytes, in a nonprotected mode (no MMU). However, using this
addressing mode may produce situations not specified in MIL-STD-1750.
Document # MICRO-2 REV G
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