PACE1750AE Datasheet, PDF (2/25 Pages) Pyramid Semiconductor Corporation – SINGLE CHIP, 20MHz to 40MHz, ENHANCED CMOS 16-BIT PROCESSOR

PACE1750AE
DIFFERENCES BETWEEN THE PACE1750A AND PACE1750AE
The PACE1750AE achieves a 41% boost in performance (in clock cycles) over the PACE1750A. This reduction in clocks
per instruction is because of three architectural enhancements:
1) The inclusion of a 24 x 24 Multiply Accumulate (MAC) array.
2) A reduction in non-bus cycles to 2 clocks (bus cycles remain at 4 clocks to maintain full compatibility with CPU’s
peripheral chips).
3) Branch calculation logic.
The table below shows how the MAC improves all multiply operations — both integer and floating point — by 477% to
760%.
Instruction
Integer Add/Sub
Double Precision Integer Add/Sub
Integer Multiply
Double Precision Integer Add/Sub
Floating Add/Sub
Extended Floating Add/Sub
Floating Multiply
Extended Floating Point Multiply
Branch (Taken)
Branch (Not Taken)
Flt’g’ Point Polynomial Step (Mul+Add/Sub)
Ext Flt’g’ Point Polynomial Step (Mul/Sub)
DAIS Mix (MIPS)
PACE1750AE
PACE1750A
Clocks Execution Clocks Execution
Gain
Time (40 MHz)
Time (40 MHz) #Clocks (%)
4
100ns
4
100ns
—
6
150ns
9
225ns
50
4
100ns
23
575ns
575
9
225ns
69
1725ns
760
18
450ns
28
700ns
55
34
850ns
51
1225ns
50
9
225ns
43
1075ns
477
17
425ns
96
2400ns
564
8
200ns
12
300ns
50
4
100ns
4
100ns
—
27
675ns
71
1775ns
263
51
1275ns
147
3675ns
2400
—
3.56
—
2.52
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PACE1750AE BUILT IN FUNCTIONS
A core set of additional instructions have been included in the PACE1750AE. These instructions utilize the Built ln Function
(BlF) opcode space. The objective of these new opcodes is to enhance the performance of the PACE in critical application
areas such as navigation, DSP, transcendentals and other LINPAK and matrix type instructions. Below is a list of the BlFs
and their execution times (N = the number of elements in the vector being processed).
Instruction
Memory Parametric Dot Product—Single
Memory Parametric Dot Product—Double
3 x 3 Register Dot Product
Double Precision Multiply Accumulate
Polynomial
Clear Accumulator
Store Accumulator (32-Bit)
Store Accumulator (48-Bit)
Load Accumulator (32-Bit)
Load Accumulator Long (48-Bit)
Move MMU Page Block
Load Timer A Reset Register
Load Timer B Reset Register
Mnemonic
VDPS
VDPD
R3DP
MACD
POLY
CLAC
STA
STAL
LAC
LACL
MMPG
LTAR
LTBR
Address
Mode
4F3(RA)
4F1(RA)
4F03
4F02
4F06
4F00
4F08
4F04
4F05
4F07
4F0F
4F0D
4F0E
Number of
Clocks
10 + 8 • N
10+16 • N
6
8
7•N-2
4
7
11
9
9
16+8 • N
4
4
Notes
Interruptable
Interruptable
Privileged
Document # MICRO-2 REV G
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