PT6314_10 Datasheet, PDF (35/42 Pages) Princeton Technology Corp – Dot Character VFD Controller/Driver IC

PT6314
11.3 TIMING 3 REQUIREMENTS
(Unless otherwise specified, Ta=-40 to +85℃); Serial Data Transfer: (VDD1=5V±10%)
Parameter
Symbol
Condition
Min.
Shift clock cycle
tCYK
SCK
500
High level shift clock pulse width
tWHK SCK
200
Low level shift clock pulse width
tWLK
SCK
200
Shift clock hold time
tHSTBK STB↓ → SCK↓
100
Data setup time
tDS
Data → SCK↑
100
Data hold time
tDH
SCK↑ → Data
100
STB hold time
tDKSTB SCK↑ → STB↑
500
STB pulse width
tWSTB
500
Wait time
tWAIT 8th CLK↑→ 1st CLK↓
1
Output data delay time
tODD SCK↓ → Data
-
Output data hold time
tODH SCK↑ → Data
5
Reset pulse width
tWRE
500
Typ.
-
-
-
-
-
-
-
-
-
-
-
-
Max. Unit
-
ns
-
ns
-
ns
-
ns
-
ns
-
ns
-
ns
-
ns
-
ns
150 ns
-
ns
-
ns
11.3.1SERIAL I/F (INPUT)
11.3.2 SERIAL I/F (OUTPUT)
Notes:
1. Input Signal Rise Time and Fall Time (tF, tR) < 15 ns.
2. All timing is specified using 0.20VDD1 and 0.80VDD1 as reference.
11.3.3 AC MEASUREMENT POINT
V1.5
35
October 2009