PT6314_10 Datasheet, PDF (20/42 Pages) Princeton Technology Corp – Dot Character VFD Controller/Driver IC

PT6314
5.8 CPU INTERFACE (DATA TRANSFER)
5.8.1 M68 PARALLEL DATA TRANSFER
The M68 type of parallel data transfer is selected when IFSEL is set to “1” and MCU is set to “0” Under this mode, the
PT6314 can interface with the CPU in 4 or 8 bits . Please take note that the internal registers are composed of 8 bits.
During data transfer in 4 bits, DB4 to DB7 performs the data transfer operation two times, the DB0 to DB3 must be set to
either “H” or “L”. The higher order 4 bits (D4 to D7) are initially transferred followed by the lower order 4 bits (D0 toD3).
please refer to the diagrams below.
4-BIT M68 TYPE PARALLEL DATA TRANSFER
8-BIT M68 TYPE PARALLEL DATA TRANSFER
V1.5
20
October 2009