PT6314_10 Datasheet, PDF (34/42 Pages) Princeton Technology Corp – Dot Character VFD Controller/Driver IC

PT6314
11.2 TIMING 2 REQUIREMENTS
(Unless otherwise specified, Ta=-40 To +85℃);i80 Interface Parallel Data Transfer: Write (VDD1=5.0 ±10%)
Parameter
Symbol
Condition
Min. Typ. Max. Unit
RS hold time
tRH8
10
-
-
ns
RS setup time
tRS8
10
-
-
ns
System cycle time
tCYC8
168 -
-
ns
Control “L” pulse width (WR)
tCCLW /WR
30
-
-
ns
Control “L” pulse width (RD)
tCCLR /RD
70
-
-
ns
Control “H” pulse width (RD)
tCCHW /WR
100 -
-
ns
Control “H” pulse width (RD)
tCCHR /RD
70
-
-
ns
Data setup time
tDS8
D0 to D7
55
-
-
ns
Data hold time
tDH8
Do to D7
55
-
-
ns
RD access time
tACC8 Do to D7, CL=100pF
-
-
70
ns
Output disable time
tOH8
Do to D7, CL=100pF
5
-
-
ns
Reset pulse width
tWRE
500 -
-
ns
11.2.1 PARALLEL I/F (i80)
Notes:
1. Input signal rise time and fall time (tF, tR) < 15ns
2. All timing is specified using 0.20VDD1 and 0.80VDD1 as reference.
3. tCCLW and tCCLR are specified as the overlap between /CS=”L” /WR and /RD=”L”
V1.5
34
October 2009