PT6314_10 Datasheet, PDF (15/42 Pages) Princeton Technology Corp – Dot Character VFD Controller/Driver IC

PT6314
5. FUNCTION DESCRIPTION
5.1 BLOCK FUNCTIONS
5.1.1 CPU INTERFACE
PT6314 provides either 4 or 8 bits parallel or serial interface. These interface modes may be selected using the IFSEL
Pin (Pin No.24) as follows:
IFSEL Setting
Data Transfer Mode
“0”
Serial Data Transfer
“1”
Parallel Data Transfer
5.1.2 REGISTERS (INSTRUCTION REGISTER & DATA REGISTER)
PT6314 supports two 8-bit registers, namely: an Instruction Register (IR) and a Data Register (DR) which may be
selected using the Register Selector (RS) Signal. Please refer to Table below
IFSEL
/CS
RS
E/SCK
R/W
MCU
SI/SO
DBn
0
/CS
STB
SCK
*
*
SI/SO
*
1
/CS
RS
E/(/RD)
R/D(/WR)
MCU
*
DBn
Note: *=This pin must be kept in either “HIGH” or “LOW” State.
The Instruction Register (IR) stores (1) instruction codes (i.e. display clear and cursor shift), (2) Display Data RAM
(DDRAM) Address Information and (3) Character Generator RAM (CGRAM). It can only be written from the MCU.
The Data Register (DR) acts as a temporary storage for (1) data to be written into the DDRAM or CGRAM and (2) data
to be read from the DDRAM or CGRAM. Data written into the DR from the MCU is automatically written into the DDRAM
or CGRAM by internal operation. When the data stored in DR is read by the MCU, data transfer is completed. After the
completion of the data transfer (that is, after the MCU has finished reading the first set of data), the DDRAM or CGRAM
data in the next address is sent to the DR. The MCU then again performs its Read operation for the next set of data.
BUSY FLAG (READ BF FLAG)
The Busy Flag Data (DB7) always outputs “0”.
ADDRESS COUNTER (AC)
The Address Counter (AC) designates the addresses of the DDRAM and CGRAM. When an address of instruction is
written into the Instruction Register, the address information is sent from the Instruction Register (IR) to the Address
Counter. The selection of either the DRAM or CGRAM is also determined concurrently by the instruction. After writing
into the DDRAM or CGRAM, the Address Counter is increased by 1. (The Address Counter is decreased by 1 after data
is read from the DDRAM or CGRAM.) The contents of the Address Counter are then outputted to the DB0~DB6 when
RS=”0” and R/W=”1”. Please refer to the table below.
Common
M68
RS
R/W
i80
/RD
/WR
Register Selection
0
0
1
0
Write IR Data as internal operation (i.e. display clear)
0
1
0
1
Read data to busy flag (DB7) and Address Counter (DB6 to DB0)
1
0
1
0
Write DR Data (DR→DDRAM/CGRAM)
1
1
0
1
Read DR Data (DDRAM/CGRAM→DR)
V1.5
15
October 2009