PT6314_10 Datasheet, PDF (27/42 Pages) Princeton Technology Corp – Dot Character VFD Controller/Driver IC

PT6314
6.7 “CGRAM ADDRESS SET” INSTRUCTION
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
CODE 0
0
0
1
A
A
A
A
A
A
The above instruction is used to (1) load new 6-bit address into the address counter, and (2) set the address counter to
point to the CGRAM.
Once the “CGRAM Address Set” instructions has been executed, the contents of the address counter (ACC) is
automatically modified after every access of the CGRAM, as determined by the ”Entry Mode Set” instruction. The active
width of the address counter, when it is addressing the CGRAM is 6 bits. The counter will wrap around from 00H to 3FH
if more than 64 bytes of data is written to the CGRAM.
During Reset, this instruction is irrelevant.
6.8 “DDRAM ADDRESS SET” INSTRUCTION
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
CODE 0
0
1
A
A
A
A
A
A
A
The above instruction is used to (1) load new 7 bits address into the address counter, and (2) set the address counter to
point to the CGRAM.
Once the “DDRAM Address Set” instruction has been executed, the contents of the address counter (ACC) is
automatically modified after every access of the DDRAM, as determined by the “Entry Mode Set” instruction. The valid
DDRAM address range is given below.
Line Display
Number of Characters
Address Range
1st Line
40
00H to 27H
2nd Line
40
40H to 67H
During Reset, this instruction is irrelevant.
6.9 “READ BUSY FLAG AND ADDRESS” INSTRUCTION
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
CODE 0
1
BF
A
A
A
A
A
A
A
The above instruction reads the Busy Flag (BF) * and the value of the address counter in binary “AAAAAAA”. This
address counter is used by the CGRAM and DDRAM addresses and its values are determined by the previous
instruction. Address counter contents are the same as that of “CGRAM Address Set” and “DDRAM Address Set”
Instructions.
Note: * The Busy Flag (BF) = “0”
6.10 “WRITE DATA TO CGRAM OR DDRAM” INSTRUCTION
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
CODE 1
0
D
D
D
D
D
A
D
D
←High Order Bit
Low Order Bit→
The above instruction write 8 bits binary data “DDDDDDDD” to the CGRAM or DDRAM.
Writing into the CGRAM or DDRAM is determined by the previous instruction of the “CGRAM or DDRAM Address Set”.
After a data is written, the value of the address is automatically increased or decreased by one in accordance to the
selection made by the “Entry Mode Set”. The “Entry Mode Set” also determines the display shift.
V1.5
27
October 2009