PE9702 Datasheet, PDF(9/13 Page) Peregrine Semiconductor Corp. – 3.0 GHz Integer-N PLL for Rad Hard Applications

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PE9702 Datasheet, PDF (9/13 Pages) Peregrine Semiconductor Corp. – 3.0 GHz Integer-N PLL for Rad Hard Applications

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PE9702

Product Specification

Serial Interface Mode

Serial Interface Mode is selected by setting the

Bmode input âlowâ and the Smode input âhighâ.

While the E_WR input is âlowâ and the S_WR

input is âlowâ, serial input data (Sdata input), B0 to

B19, is clocked serially into the primary register on

the rising edge of Sclk, MSB (B0) first. The

contents from the primary register are transferred

into the secondary register on the rising edge of

either S_WR or Hop_WR according to the timing

diagram shown in Figure 6. Data is transferred to

the counters as shown in Table 7.

The double buffering provided by the primary and

secondary registers allows for âping-pongâ counter

control using the FSELS input. When FSELS is

âhighâ, the primary register contents set the

counter inputs. When FSELS is âlowâ, the

secondary register contents are utilized.

While the E_WR input is âhighâ and the S_WR

input is âlowâ, serial input data (Sdata input), B0 to

B7, is clocked serially into the enhancement

The enhancement register is double buffered to

prevent inadvertent control changes during serial

loading, with buffer capture of the serially-entered

data performed on the falling edge of E_WR

according to the timing diagram shown in

Figure 5. After the falling edge of E_WR, the data

provides control bits as shown in Table 8 with bit

functionality enabled by asserting the Enh input

âlowâ.

Direct Interface Mode

Direct Interface Mode is selected by setting the

Bmode input âhighâ.

Counter control bits are set directly at the pins as

shown in Table 7. In Direct Interface Mode, main

counter inputs M7 and M8, and R Counter inputs

R4 and R5 are internally forced low (â0â).

Table 7. Primary Register Programming

Interface

Mode

Enh

Bmode Smode R5

M8 M7 Pre_en M6

M5 M4

M0 R3 R2 R1 R0 A3 A2 A1 A0

M2_WR rising edge load

M1_WR rising edge load

A_WR rising edge load

Parallel 1

D0 D7 D6 D5 D4 D3 D2 D1 D0

Serial*

B10

B11

B12 B13 B14 B15 B16 B17 B18 B19

Direct

0 Pre_en M6 M5 M4 M3 M2 M1 M0 R3 R2 R1 R0 A3 A2 A1 A0

*Serial data clocked serially on Sclk rising edge while E_WR âlowâ and captured in secondary register on S_WR rising edge.

MSB (first in)

(last in) LSB

Table 8. Enhancement Register Programming

Interface

Mode

Enh

Bmode Smode

Reserved

Parallel 0

Serial*

Power

down

Counter

load

E_WR rising edge load

MSEL

output

Prescaler

output

*Serial data clocked serially on Sclk rising edge while E_WR âhighâ and captured in the double buffer on E_WR falling edge.

fc, fp OE

MSB (first in)

(last in) LSB

Document No. 70-0036-02 â www.psemi.com

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