PE9702 Datasheet, PDF (3/13 Pages) Peregrine Semiconductor Corp. – 3.0 GHz Integer-N PLL for Rad Hard Applications

PE9702
Product Specification
Table 1. Pin Descriptions (continued)
Pin No. Pin Name Interface Mode Type
Sdata
Serial
Input
14
D5
Parallel
Input
M5
Direct
Input
Sclk
Serial
Input
15
D6
Parallel
Input
M6
Direct
Input
FSELS
Serial
Input
16
D7
Parallel
Pre_en
Direct
Input
Input
17
GND
ALL
FSELP
Parallel
18
A0
Direct
Input
Input
Serial
E_WR
19
Parallel
Input
Input
A1
Direct
Input
M2_WR
Parallel
20
A2
Direct
Input
Input
Smode
Serial, Parallel
Input
21
A3
Direct
Input
22
Bmode
ALL
Input
23
VDD
ALL
(Note 1)
24
M1_WR
Parallel
Input
25
A_WR
Parallel
Input
26
Hop_WR
Serial, Parallel
Input
27
Fin
ALL
Input
28
F_in
ALL
Input
29
GND
ALL
30
fp
ALL
Output
Description
Binary serial data input. Input data entered MSB first.
Parallel data bus bit5.
M Counter bit5.
Serial clock input. Sdata is clocked serially into the 20-bit primary register (E_WR
“low”) or the 8-bit enhancement register (E_WR “high”) on the rising edge of Sclk.
Parallel data bus bit6.
M Counter bit6.
Selects contents of primary register (FSELS=1) or secondary register (FSELS=0) for
programming of internal counters while in Serial Interface Mode.
Parallel data bus bit7 (MSB).
Prescaler enable, active “low”. When “high”, Fin bypasses the prescaler.
Ground.
Selects contents of primary register (FSELP=1) or secondary register (FSELP=0) for
programming of internal counters while in Parallel Interface Mode.
A Counter bit0 (LSB).
Enhancement register write enable. While E_WR is “high”, Sdata can be serially
clocked into the enhancement register on the rising edge of Sclk.
Enhancement register write. D[7:0] are latched into the enhancement register on the
rising edge of E_WR.
A Counter bit1.
M2 write. D[3:0] are latched into the primary register (R[5:4], M[8:7]) on the rising
edge of M2_WR.
A Counter bit2.
Selects serial bus interface mode (Bmode=0, Smode=1) or Parallel Interface Mode
(Bmode=0, Smode=0).
A Counter bit3 (MSB).
Selects direct interface mode (Bmode=1).
Same as pin 1.
M1 write. D[7:0] are latched into the primary register (Pre_en, M[6:0]) on the rising
edge of M1_WR.
A write. D[7:0] are latched into the primary register (R[3:0], A[3:0]) on the rising edge
of A_WR.
Hop write. The contents of the primary register are latched into the secondary
register on the rising edge of Hop_WR.
Prescaler input from the VCO. 3.0 GHz max frequency.
Prescaler complementary input. A bypass capacitor in series with a 51 Ω resistor
should be placed as close as possible to this pin and be connected directly to the
ground plane.
Ground.
Monitor pin for main divider output. Switching activity can be disabled through
enhancement register programming or by floating or grounding VDD pin 31.
Document No. 70-0036-02 │ www.psemi.com
©2003-2006 Peregrine Semiconductor Corp. All rights reserved.
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