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PE9702 Datasheet, PDF (2/13 Pages) Peregrine Semiconductor Corp. – 3.0 GHz Integer-N PLL for Rad Hard Applications
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PE9702
Product Specification
Figure 2. Pin Configurations (Top View)
D0, M0
D1, M1
D2, M2
D3, M3
VDD
VDD
S_W R, D4, M4
Sdata, D5, M5
Sclk, D6, M6
FSELS, D7, Pre_en
GND
6 5 4 3 2 1 44 43 42 41 40
7
39
8
38
9
37
10
36
11
35
12
34
13
33
14
32
15
31
16
30
17
29
18 19 20 21 22 23 24 25 26 27 28
fc
VDD_fc
PD_U
PD_D
VDD
Cext
VDD
Dout
VDD_fp
fp
GND
Figure 3. Package Type
44-lead CQFJ
Table 1. Pin Descriptions
Pin No. Pin Name Interface Mode
1
VDD
ALL
2
R0
Direct
3
R1
Direct
4
R2
Direct
5
R3
Direct
6
GND
ALL
D0
7
M0
Parallel
Direct
8
D1
Parallel
M1
Direct
9
D2
Parallel
M2
Direct
10
D3
Parallel
M3
Direct
11
VDD
ALL
12
VDD
ALL
Type
(Note 1)
Input
Input
Input
Input
(Note 1)
Input
Input
Input
Input
Input
Input
Input
Input
(Note 1)
(Note 1)
S_WR
Serial
13
D4
Parallel
M4
Direct
Input
Input
Input
Description
Power supply input. Input may range from 2.85 V to 3.15 V. Bypassing
recommended.
R Counter bit0 (LSB).
R Counter bit1.
R Counter bit2.
R Counter bit3.
Ground.
Parallel data bus bit0 (LSB).
M Counter bit0 (LSB).
Parallel data bus bit1.
M Counter bit1.
Parallel data bus bit2.
M Counter bit2.
Parallel data bus bit3.
M Counter bit3.
Same as pin 1.
Same as pin 1.
Serial load enable input. While S_WR is “low”, Sdata can be serially clocked.
Primary register data is transferred to the secondary register on S_WR or Hop_WR
rising edge.
Parallel data bus bit4
M Counter bit4
©2003-2006 Peregrine Semiconductor Corp. All rights reserved.
Page 2 of 13
Document No. 70-0036-02 │ UltraCMOS™ RFIC Solutions
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