ZY7007 Datasheet, PDF (7/35 Pages) Power-One – 7A DC-DC Intelligent POL 3V to 14V Input - 0.5V to 5.5V Output

ZY7007 7A DC-DC Intelligent POL Data Sheet
3V to 14V Input • 0.5V to 5.5V Output
4.5 Signal Specifications
Parameter
VDD
Conditions/Description
Min
Internal supply voltage
3.15
SYNC/DATA Line (SD pin)
ViL_sd
ViH_sd
Vhyst_sd
VoL
LOW level input voltage
HIGH level input voltage
Hysteresis of input Schmitt trigger
LOW level sink current @ 0.5V
-0.5
0.75 x
VDD
0.25 x
VDD
14
Tr_sd
Cnode_sd
Maximum allowed rise time 10/90%VDD
Added node capacitance
Ipu_sd
Pull-up current source at Vsd=0V
0.3
Freq_sd
Clock frequency of external SD line
475
Tsynq
Sync pulse duration
22
T0
ViL_x
ViH_x
Vhyst_x
RdnL_ADDR
Iup_PG
Iup_OK
ViL_x
ViH_x
Vhyst_x
IoL
Iup_CS
ViL_CS
ViH_CS
Vhyst_CS
IoL
Tr_CS
Data=0 pulse duration
72
Inputs: ADDR0…ADDR4, EN, IM
LOW level input voltage
-0.5
HIGH level input voltage
0.7 x VDD
Hysteresis of input Schmitt trigger
0.1 x VDD
External pull down resistance
ADDRX forced low
Power Good and OK Inputs/Outputs
Pull-up current source input forced low PG
25
Pull-up current source input forced low OK
175
LOW level input voltage
-0.5
HIGH level input voltage
0.7 x VDD
Hysteresis of input Schmitt trigger
0.1 x VDD
LOW level sink current at 0.5V
4
Current Share Bus (CS pin)
Pull-up current source at VCS = 0V
0.84
LOW level input voltage
HIGH level input voltage
Hysteresis of input Schmitt trigger
LOW level sink current at 0.5V
-0.5
0.75 x
VDD
0.25 x
VDD
14
Maximum allowed rise time 10/90% VDD
Nom
3.3
5
Max
Units
3.45
V
0.3 x VDD
V
VDD + 0.5
V
0.45 x
VDD
V
60
mA
300
ns
10
pF
1.0
mA
525
kHz
28
% of clock
cycle
78
% of clock
cycle
0.3 x VDD
VDD+0.5
0.3 x VDD
10
V
V
V
kOhm
110
μA
725
μA
0.3 x VDD
V
VDD+0.5
V
0.3 x VDD
V
20
mA
3.1
mA
0.3 x VDD
V
VDD+0.5
V
0.45 x
VDD
V
60
mA
100
ns
ZD-00245 REV. 2.5
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