ZY7007 Datasheet, PDF (21/35 Pages) Power-One – 7A DC-DC Intelligent POL 3V to 14V Input - 0.5V to 5.5V Output

ZY7007 7A DC-DC Intelligent POL Data Sheet
3V to 14V Input • 0.5V to 5.5V Output
R/W-0
LR2
Bit 7
R/W-0
LR1
R/W-0
LR0
R/W-1
TCE
R/W-1
CLS3
R/W-0
CLS2
R/W-1
CLS1
R/W-1
CLS0
Bit 0
Bit 7:5 LR[2:0], Load regulation configuration
000: 0 V/A/Ohm
001: 0.39 V/A/Ohm
010: 0.78 V/A/Ohm
011: 1.18 V/A/Ohm
100: 1.57 V/A/Ohm
101: 1.96 V/A/Ohm
110: 2.35 V/A/Ohm
111: 2.75 V/A/Ohm
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
Bit 4
TCE, Temperature compensation enable
0: disabled
1: enabled
Bit 3:0 CLS[3:0], Current limit setting
0h: corresponds to 37%
1h: corresponds to 47%
…
Bh: corresponds to 140%
Values higher than Bh are translated to Bh (140%)
Figure 36. Current Limit Setpoint Register CLS
U
U
---
---
Bit 7
U
R/W-0 R/W-1 R/W-0 R/W-0 R/W-0
---
PGLL OVPL1 OVPL0 UVPL1 UVPL0
Bit 0
Bit 7:5 Unimplemented, read as ‘0’
Bit 4 PGLL: Set Power Good Low Level
1 = 95% of Vo
0 = 90% of Vo (Default)
Bit 3:2 OVPL[1:0]: Set Over Voltage Protection
Level
00 = 110% of Vo
01 = 120% of Vo
10 = 130% of Vo (Default)
11 = 130% of Vo
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
Bit 1:0 UVPL[1:0]: Set Under Voltage Protection Level
00 = 75% of Vo (Default)
01 = 80% of Vo
10 = 85% of Vo
Figure 37. Protection Configuration Register PC2
Note that the overvoltage and undervoltage
protection thresholds and Power Good limits are
defined as percentages of the output voltage.
Therefore, the absolute levels of the thresholds
change when the output voltage setpoint is changed
either by output voltage adjustment or by margining.
In addition, a user can change type of protections
(latching or non-latching) or disable certain
protections. These settings are programmed in the
GUI Fault Management window shown in Figure 38
or directly via the I²C by writing into the PC1 register
shown in Figure 39.
Figure 38. Fault Management Window
R/W-0
TRE
Bit 7
R/W-1
PVE
R/W-0
TRP
R/W-0
OTP
R/W-0
OCP
R/W-0
UVP
R/W-1
OVP
R/W-1
PVP
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TRE: Tracking fault enable
1 = enabled
0 = disabled
PVE: Phase voltage error enable
1 = enabled
0 = disabled
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
TRP: Tracking fault protection
1 = latching
0 = non latching
OTP: Overtemperature protection configuration
1 = latching
0 = non latching
OCP: Overcurrent protection configuration
1 = latching
0 = non latching
UVP: Undervoltage protection configuration
1 = latching
0 = non latching
OVP: Overvoltage protection configuration
1 = latching
0 = non latching
PVP: Phase Voltage Protection
1 = latching
0 = non latching
Figure 39. Protection Configuration Register PC1
If the non-latching protection is selected, a POL will
attempt to restart every 130ms until the condition
that triggered the protection is removed. When
restarting, the output voltages follow tracking and
sequencing settings.
If the latching type is selected, a POL will turn off and
stay off. The POL can be turned on after 130ms, if
the condition that caused the fault is removed and
the respective bit in the ST register was cleared, or
the Turn On command was recycled, or the input
voltage was recycled.
ZD-00245 REV. 2.5
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