ZY7007 Datasheet, PDF (27/35 Pages) Power-One – 7A DC-DC Intelligent POL 3V to 14V Input - 0.5V to 5.5V Output

ZY7007 7A DC-DC Intelligent POL Data Sheet
3V to 14V Input • 0.5V to 5.5V Output
Figure 48 shows the input voltage noise of the three-
output system with programmed interleave. Instead
of all three POLs switching at the same time as in
the previous example, the POLs V1, V2, and V3
switch at 67.5°, 180°, and 303.75°, respectively.
Noise is spread evenly across the switching cycle
resulting in more than 1.5 times reduction. To
achieve similar noise reduction without the interleave
will require the addition of an external LC filter.
Figure 48. Input Voltage Noise with Interleave
Similar noise reduction can be achieved on the
output of POLs connected in parallel. Figure 49 and
Figure 50 show the output noise of two ZY7007s
connected in parallel without and with 180°
interleave, respectively. Resulting noise reduction is
more than 2 times and is equivalent to doubling
switching frequency or adding extra capacitance on
the output of the POLs.
Figure 49. Output Voltage Noise, Full Load, No Interleave
Figure 50. Output Voltage Noise, Full Load, 180° Interleave
The ZY7007 interleave feature is similar to that of
multiphase converters, however, unlike in the case of
multiphase converters, interleave does not have to
be equal to 360/N, where N is the number of POLs in
a system. ZY7007 interleave is independent of the
number of POLs in a system and is fully
programmable in 11.25° steps. It allows maximum
output noise reduction by intelligently spreading
switching energy.
Note: Due to noise sensitivity issues that may occur in limited
cases, it is recommended to avoid phase lag settings of
112.5 and 123.75 degrees, otherwise false PG and/or OV
indications may occur.
8.4.3 Duty Cycle Limit
The ZY7007 is a step-down converter therefore V_OUT
is always less than V_IN. The relationship between
the two parameters is characterized by the duty
cycle and can be estimated from the following
equation:
DC = ^VOUT ,
V_IN.MIN
Where, DC is the duty cycle, V_OUT is the required
maximum output voltage (including margining),
V_IN.MIN is the minimum input voltage.
It is good practice to limit the maximum duty cycle of
the PWM controller to a somewhat higher value
compared to the steady-state duty cycle as
expressed by the above equation. This will further
protect the output from excessive voltages. The duty
cycle limit can be programmed in the GUI PWM
ZD-00245 REV. 2.5
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