PM7382 Datasheet, PDF (97/330 Pages) PMC-Sierra, Inc – Frame Engine and Data Link Manager 32P256

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DATA SHEET
PMC-2010333
ISSUE 3
PM7382 FREEDM-32P256
FRAME ENGINE AND DATA LINK MANAGER 32P256
PCI Offset
Register
0x480 - 0x4FC
0x500
0x504
0x508
TCAS Link #0 through #31 Configuration
PMON Status
PMON Receive FIFO Overflow Count
PMON Transmit FIFO Underflow Count
0x50C
0x510
0x514 - 0x51C
0x520 - 0x7FC
PMON Configurable Count #1
PMON Configurable Count #2
PMON Reserved
Reserved
The following PCI configuration registers are implemented by the PCI Interface.
These registers can only be accessed when the PCI Interface is a target and a
configuration cycle is in progress as indicated using the IDSEL input.
Table 13 – PCI Configuration Register Memory Map
PCI Offset
0x00
0x04
0x08
0x0C
0x10
0x14 - 0x24
0x28 - 0x38
0x3C
Register
Vendor Identification/Device Identification
Command/Status
Revision Identifier/Class Code
Cache Line Size/Latency Timer/Header Type/BIST
CBI Memory Base Address Register
Unused Base Address Register
Reserved
Interrupt Line/Interrupt Pin/MIN_GNT/MAX_LAT
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 86