PM7382 Datasheet, PDF (217/330 Pages) PMC-Sierra, Inc – Frame Engine and Data Link Manager 32P256

RELEASED
DATA SHEET
PMC-2010333
ISSUE 3
PM7382 FREEDM-32P256
FRAME ENGINE AND DATA LINK MANAGER 32P256
Register 0x334 : TMAC Descriptor Reference Ready Queue End
Bit
Bit 31
to
Bit 16
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
Unused
Default
XXXXH
TDRRQE[15]
0
TDRRQE[14]
0
TDRRQE[13]
0
TDRRQE[12]
0
TDRRQE[11]
0
TDRRQE[10]
0
TDRRQE[9]
0
TDRRQE[8]
0
TDRRQE[7]
0
TDRRQE[6]
0
TDRRQE[5]
0
TDRRQE[4]
0
TDRRQE[3]
0
TDRRQE[2]
0
TDRRQE[1]
0
TDRRQE[0]
0
This register provides the Transmit Descriptor Reference Ready Queue end
address.
Note
This register is not byte addressable. Writing to this register modifies all the bits
in the register. Byte selection using byte enable signals (CBEB[3:0]) are not
implemented. However, when all four byte enables are negated, no access is
made to this register.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 206