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PM7382 Datasheet, PDF (85/330 Pages) PMC-Sierra, Inc – Frame Engine and Data Link Manager 32P256
RELEASED
DATA SHEET
PMC-2010333
ISSUE 3
PM7382 FREEDM-32P256
FRAME ENGINE AND DATA LINK MANAGER 32P256
packet P3. The TMAC256 indicates valid horizontal links by setting the V bit to
logic 1.
8.7.2 Task Priorities
The TMAC256 must perform a number of tasks concurrently in order to maintain
a steady flow of data through the system. The main tasks of the TMAC256 are
managing the Ready Queue (i.e. removing chains of data packets from the
queue and attaching them to the appropriate per-channel linked list) and
servicing requests for data from the Transmit Packet Interface. The priority of
service for each of the tasks is fixed by the TMAC256 as follows:
· Top priority is given to servicing ‘expedited’ read requests from the Transmit
HDLC Processor / Partial Packet Buffer block (THDL256).
· Second priority is given to removing chains of data packets from the TDRR
queue and attaching them to the appropriate per-channel linked list.
· Third priority is given to servicing non-expedited read requests from the
THDL256.
8.7.3 DMA Transaction Controller
The DMA Transaction Controller coordinates the processing of requests from the
THDL256 with the reading of data stored in host memory. The reading of a data
packet may require a number of separate host memory transactions, interleaved
with transactions of other DMA channels. As well as reading data from the Host
Master Interface, the DMA Transaction Controller initiates read and write
transactions to the PCI Controller block (GPIC) for the purposes of maintaining
the data structures (queues, descriptors, etc.) in host memory.
8.7.4 Read Data Pipeline
The Read Data Pipeline inserts delay in the data stream between the GPIC
interface and the THDL256 interface to enable the DMA Transaction Controller to
generate appropriate control signals at the Transmit Packet Interface.
8.7.5 Descriptor Information Cache
The Descriptor Information Cache provides the storage for the Transmit Channel
Descriptor Reference (TCDR) Table.
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