PM7382 Datasheet, PDF (180/330 Pages) PMC-Sierra, Inc – Frame Engine and Data Link Manager 32P256

RELEASED
DATA SHEET
PMC-2010333
ISSUE 3
PM7382 FREEDM-32P256
FRAME ENGINE AND DATA LINK MANAGER 32P256
2. If consecutive write accesses to this register are performed, they must be
spaced at least 4 SYSCLK periods apart.
RPDRSFQW[15:0]:
The receive packet descriptor reference (RPDR) small buffer free queue write
bits (RPDRSFQW[15:0]) define bits 17 to 2 of the Receive Packet Descriptor
Reference Small Buffer Free Queue write pointer. This register is initialised
by the host. The physical write address in the RPDRSF queue is the sum of
RPDRSFQW[15:0] left shifted by 2 bits with the RQB[31:0] bits in the RMAC
Receive Queue Base register.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 169