PM7382 Datasheet, PDF (90/330 Pages) PMC-Sierra, Inc – Frame Engine and Data Link Manager 32P256

RELEASED
DATA SHEET
PMC-2010333
ISSUE 3
PM7382 FREEDM-32P256
FRAME ENGINE AND DATA LINK MANAGER 32P256
an associated data clock frequency that is double the data rate. This provides
more bandwidth per link for applications requiring higher data densities on a
single link. Data at each time-slot may be independently assigned to be sourced
from a different channel. Second, H-MVIP links reference the start of each
frame with a frame pulse, thereby avoiding having to gap the link clock during the
framing bits/bytes of each frame. The frame pulse is provided by an H-MVIP bus
master and ensures that all agents sharing the H-MVIP bus remain
synchronized. When configured for operation in 2.048 Mbps H-MVIP mode, the
frame pulse is sampled using the same clock which samples the data. When
configured for operation in 8.192 Mbps H-MVIP mode, the frame pulse is
sampled using a separate frame pulse clock provided by an H-MVIP bus master.
The frame pulse clock has a synchronous timing relationship to the data clock.
Third, not all links are independent. When configured for operation in 2.048
Mbps H-MVIP mode, each group of 8 links share a clock and a frame pulse.
Links 0 through 7, 8 through 15, 16 through 23 and 24 through 31 each share a
clock and a frame pulse. Not all 8 links within each group need to be configured
for operation in 2.048 Mbps H-MVIP mode. However, any link within each logical
group of 8 which is configured for 2.048 Mbps H-MVIP operation will share the
same clock and frame pulse. When configured for operation in 8.192 Mbps H-
MVIP mode, links 4m (0£m£7) share a frame pulse, a data clock and a frame
pulse clock. Again, not all eight 4m (0£m£7) links need to be configured for
operation in 8.192 Mbps H-MVIP mode, however, any link which is configured for
8.192 Mbps H-MVIP operation will share the same frame pulse, data clock and
frame pulse clock. If link 4m is configured for 8.192 Mbps H-MVIP operation,
then data transferred on that link is “spread” over links 4m, 4m+1 4m+2 and
4m+3 from a channel assigner point of view. Accordingly, when link 4m is
configured for operation in 8.192 Mbps H-MVIP mode, links 4m+1, 4m+2 and
4m+3 must also be configured for operation in 8.192 Mbps H-MVIP mode. In the
back end, the TCAS256 extracts and processes the time-slots identically to
channelised T1/J1/E1 traffic.
Links containing a T1/J1 or an E1 stream may be channelised. Data at each
time-slot may be independently assigned to be sourced from a different channel.
The link clock is only active during time-slots 1 to 24 of a T1/J1 stream and is
inactive during the frame bit. Similarly, the clock is only active during time-slots 1
to 31 of an E1 stream and is inactive during the FAS and NFAS framing bytes.
The most significant bit of time-slot 1 of a channelised link is identified by noting
the absence of the clock and its re-activation. With knowledge of the transmit
link and time-slot identity, the TCAS256 performs a table look-up to identify the
channel from which a data byte is to be sourced.
Links may also be unchannelised. Then, all data bytes on that link belong to one
channel. The TCAS256 performs a table look-up to identify the channel to which
a data byte belongs using only the outgoing link identity, as no time-slots are
associated with unchannelised links. Link clocks are no longer limited to T1/J1
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 79