PM6388 Datasheet, PDF (204/345 Pages) PMC-Sierra, Inc – Octal E1 Framer

DATA SHEET
PMC-1971019
ISSUE 6
PM6388 EOCTL
OCTAL E1 FRAMER
Register 053H, 0D3H, 153H, 1D3H, 253H, 2D3H ,353H, 3D3H: TDPR #1,
#2, #3 Interrupt Enable
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R/W
R/W
R/W
R/W
R/W
Function
Unused
Unused
Unused
Reserved
FULLE
OVRE
UDRE
LFILLE
Default
X
X
X
0
0
0
0
0
Selection of the TDPR block (#1, #2, or #3) whose registers are visible on the
microprocessor interface is done via the TDPRSEL[1:0] register bits in the Data
Link Micro Select/Framer Reset register.
LFILLE:
The LFILLE enables a transition to logic 1 on LFILLI to generate an interrupt
on INTB. If LFILLE is a logic 1, a transition to logic 1 on LFILLI will generate
an interrupt on INTB. If LFILLE is a logic 0, a transition to logic 1 on LFILLI
will not generate an interrupt on INTB.
UDRE:
The UDRE enables a transition to logic 1 on UDRI to generate an interrupt on
INTB. If UDRE is a logic 1, a transition to logic 1 on UDRI will generate an
interrupt on INTB. If UDRE is a logic 0, a transition to logic 1 on UDRI will not
generate an interrupt on INTB.
OVRE:
The OVRE enables a transition to logic 1 on OVRI to generate an interrupt on
INTB. If OVRE is a logic 1, a transition to logic 1 on OVRI will generate an
interrupt on INTB. If OVRE is a logic 0, a transition to logic 1 on OVRI will not
generate an interrupt on INTB.
FULLE:
The FULLE enables a transition to logic 1 on FULLI to generate an interrupt
on INTB. If FULLE is a logic 1, a transition to logic 1 on FULLI will generate
PROPRIETARY and CONFIDENTIAL to PMC-Sierra Inc. and for its customers’ internal use
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