PM6388 Datasheet, PDF (119/345 Pages) PMC-Sierra, Inc – Octal E1 Framer

DATA SHEET
PMC-1971019
ISSUE 6
PM6388 EOCTL
OCTAL E1 FRAMER
Registers 019H, 099H, 119H, 199H, 219H, 299H, 319H, 399H: Transmit
Backplane Frame Pulse Configuration
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R/W
R/W
R/W
R/W
R/W
Function
Reserved
Unused
Unused
Unused
FPINV
Reserved
FPTYP
Reserved
Default
0
X
X
X
0
0
0
1
Reserved:
This register bit must be set to logic 0 for proper operation.
FPINV:
The frame pulse inversion (FPINV) bit determines whether CIFP is inverted
prior to sampling. If FPINV is a logic 0, CIFP is active high. If FPINV is a
logic 1, CEFP is active low.
Reserved:
This register bit must be set to logic 0 for proper operation.
FPTYP:
The frame pulse type (FPTYP) bit determines the type of frame pulse
expected on CEFP. When FPTYP is a logic 0, basic frame alignment is
chosen and frame pulses are expected every frame. When FPTYP is a
logic 1, multiframe alignment is chosen.
With multiframe alignment, CEFP must be brought high to mark bit 1 of frame
1 of every 16 frame signaling multiframe and brought low following bit 1 of
frame 1 of every 16 frame CRC multiframe.
Reserved:
This register bit must be set to logic 1 for proper operation.
PROPRIETARY and CONFIDENTIAL to PMC-Sierra Inc. and for its customers’ internal use
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