PM6388 Datasheet, PDF (125/345 Pages) PMC-Sierra, Inc – Octal E1 Framer

DATA SHEET
PMC-1971019
ISSUE 6
PM6388 EOCTL
OCTAL E1 FRAMER
Registers 020H, 0A0H, 120H, 1A0H, 220H, 2A0H, 320H, 3A0H: RJAT
Interrupt Status
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R
R
Function
Unused
Unused
Unused
Unused
Unused
Unused
OVRI
UNDI
Default
X
X
X
X
X
X
X
X
These registers contain the indication of the RJAT FIFO status.
OVRI:
The OVRI bit is asserted when an attempt is made to write data into the FIFO
when the FIFO is already full. When OVRI is a logic 1, an overrun event has
occurred. The OVRI bit is cleared after this register is read.
UNDI:
The UNDI bit is asserted when an attempt is made to read data from the
FIFO when the FIFO is already empty. When UNDI is a logic 1, an underrun
event has occurred. The UNDI bit is cleared after this register is read.
PROPRIETARY and CONFIDENTIAL to PMC-Sierra Inc. and for its customers’ internal use
106