PM6388 Datasheet, PDF (150/345 Pages) PMC-Sierra, Inc – Octal E1 Framer

DATA SHEET
PMC-1971019
ISSUE 6
PM6388 EOCTL
OCTAL E1 FRAMER
Register 02CH, 0ACH, 12CH, 1ACH, 22CH, 2ACH, 32CH, 3ACH (TXCISEL
= 1): TXCI Transmit Data Link 3 Control
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
DL3_EVEN
DL3_ODD
Unused
DL3_TS[4]
DL3_TS[3]
DL3_TS[2]
DL3_TS[1]
DL3_TS[0]
Default
0
0
X
0
0
0
0
0
This register controls the insertion of the data link generated by TDPR #3 into the
transmit data stream. Refer to the “Using the Internal HDLC Transmitters”
description in the Operation section for details on sourcing HDLC frames.
DL3_EVEN:
This data link 3 even select (DL3_EVEN) bit controls whether or not the data
link from TDPR#3 is inserted into the chosen timeslot of even frames of the
data stream. If DL3_EVEN is a logic 0, the data link is not inserted into the
even frames. If DL3_EVEN is a logic 1, the data link is inserted into the even
frames. Even/odd frames are set by the CRC multiframe alignment. The
FAS Bits are contained in the even frames.
DL3_ODD:
This data link 3 odd select (DL3_ODD) bit controls whether or not the data
link from TDPR#3 is inserted into the chosen timeslot of odd frames of the
data stream. If DL3_ODD is a logic 0, the data link is not inserted into the
odd frames. If DL3_ODD is a logic 1, the data link is inserted into the odd
frames. Even/odd frames are set by the CRC multiframe alignment. The
National Bits are contained in the odd frames.
PROPRIETARY and CONFIDENTIAL to PMC-Sierra Inc. and for its customers’ internal use
131