PL580-30 Datasheet, PDF (8/9 Pages) PhaseLink Corporation – 38MHz-640MHz Low Phase Noise VCXO

9. PECL Electrical Characteristics
PARAMETERS
Output High Voltage
Output Low Voltage
SYMBOL
VOH
VOL
(Preliminary) PL580-30
38MHz-640MHz Low Phase Noise VCXO
CONDITIONS
RL = 50 Ω to (VDD – 2V)
(see figure)
MIN.
VDD – 1.025
MAX.
VDD – 1.620
UNITS
V
V
11. PECL Switching Characteristics
PARAMETERS
SYMBOL
FREQ.
CONDITIONS MIN. TYP. MAX. UNITS
Clock Rise & Fall Times
Clock Rise & Fall Times
Clock Rise & Fall Times
<150MHz
0.2
0.5
0.7
tr & tf
>150MHz
<320MHz
@20/80% - PECL
@80/20% - PECL
0.2
0.4
0.55
ns
>320MHz
0.2
0.3
0.45
PECL Levels Test Circuit
OUT
VDD
50Ω
2.0V
PECL Output Skew
OUT
50%
50Ω
OUT
OUT
t_SKEW
PECL Transistion Time Waveform
DUTY CYCLE
45 - 55%
55 - 45%
OUT
80%
50%
20%
OUT
t_R
t_F
11. CMOS Electrical Characteristics
PARAMETERS
Output drive current
Output Clock Rise/Fall Time
Output Clock Rise/Fall Time
SYMBOL
IOH
IOL
CONDITIONS
VOH= VDD-0.4V, VDD=3.3V
VOL = 0.4V, VDD = 3.3V
0.3V ~ 3.0V with 15 pF load
20%-80% with 50Ω Load
MIN.
30
30
TYP. MAX.
0.7
0.3
UNITS
mA
mA
ns
ns
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