PL580-30 Datasheet, PDF (6/9 Pages) PhaseLink Corporation – 38MHz-640MHz Low Phase Noise VCXO

(Preliminary) PL580-30
38MHz-640MHz Low Phase Noise VCXO
4. General Electrical Specifications
PARAMETERS SYMBOL
CONDITIONS
Supply Current,
Dynamic (with
Loaded Outputs)
38MHz<Fout<100MHz
PECL/LVDS/CMOS
IDD
100MHz<Fout<320MHz
PECL/LVDS
320MHz<Fout<640MHz
Operating Voltage
VDD
Output Clock
Duty Cycle
@ 50% VDD (CMOS)
@ 1.25V (LVDS)
@ VDD – 1.3V (PECL)
Short Circuit
Current
Note: CMOS operation is not advised above 200MHz with 15pF load; and 320MHz with 10pF load.
MIN.
2.97
45
45
45
TYP.
50
50
50
±50
MAX.
65/45/30
80/60/40
90/70
3.63
55
55
55
UNITS
mA
V
%
mA
5. Jitter Specifications
PARAMETERS
CONDITIONS
Integrated jitter RMS
Integrated 12 kHz to 20 MHz
Period jitter RMS
With capacitive decoupling
between VDD and GND.
Over 10,000 cycles.
Period jitter Peak-to-
Peak
With capacitive decoupling
between VDD and GND.
Over 10,000 cycles.
FREQUENCY
155.52MHz
311.04MHz
622.08MHz
77.76MHz
155.52MHz
311.04MHz
622.08MHz
77.76MHz
155.52MHz
311.04MHz
622.08MHz
MIN.
TYP.
0.4
0.4
0.4
2.5
3
3
6
18
20
25
40
MAX.
0.5
0.5
0.5
4
5
5
8
30
30
30
50
UNITS
ps
ps
ps
6. Phase Noise Specifications
PARAMETERS
FREQ. @10Hz
77.76MHz
-66
Phase Noise
155.52MHz -62
relative to carrier
(typical)
311.04MHz -59
622.08MHz -48
Note: Phase Noise measured at VCON = 0V.
@100Hz
-96
-92
-86
-80
@1kHz
-124
-120
-116
-108
@10kHz
-136
-132
-129
-118
@100kHz
-132
-128
-124
-114
@1M
-145
-144
-140
-131
@10M
-149
-150
-148
-138
UNITS
dBc/Hz
47745 Fremont Blvd., Fremont, California 94538 Tel [phone] Fax [phone] www.phaselink.com Rev 11/30/05 Page 6