PL580-30 Datasheet, PDF (1/9 Pages) PhaseLink Corporation – 38MHz-640MHz Low Phase Noise VCXO

(Preliminary) PL580-30
38MHz-640MHz Low Phase Noise VCXO
FEATURES
• Less than 0.4ps RMS (12KHz-20MHz) phase
jitter for all frequencies.
• Low phase noise output (@ 1MHz frequency
offset
∗ -140dBc/Hz for 311.04MHz,
∗ -131dBC/Hz for 622.08MHz
• 19MHz-40MHz crystal input.
• 38MHz-640MHz output.
• Selectable PECL, LVDS, or CMOS outputs.
• No external varicap required.
• Output Enable selector.
• Wide pull range (+/-200ppm).
• 3.3V operation.
• Available in 3x3 QFN or 16-pin TSSOP
packages.
DESCRIPTION
The PL580-30 is a monolithic low jitter and low
phase noise VCXO, capable of 0.4ps RMS phase
jitter and PECL, LVDS, or CMOS outputs, covering a
wide frequency output range up to 640MHz. It allows
the control of the output frequency with an input
voltage (VCON), using a low cost crystal.
The PL580-30 is designed to address the demanding
requirements of high performance applications such
as SONET, GPS, XDSL, etc.
DIE CONFIGURATION
65 mil
(1550,1475)
25
24 23 22 21
20
19
18
17 GNDBUF
XIN 26
XOUT 27
Die ID:
2222-22A
16 CMOS
15 LVDSB
SEL2 28
14 PECLB
DNC 29
13 VDDBUF
12 VDDBUF
OE_CTRL 30
C502A
11 PECL
10 LVDS
VCON 31
9 OE_SEL^
12345
6
78
Y
(0,0)
X
Note1: ^ Denotes internal pull up resistor.
DIE SPECIFICATIONS
BLOCK DIAGRAM
Name
Size
Reverse side
Pad dimensions
Thickness
Value
62 x 65 mil
GND
80 micron x 80 micron
10 mil
VCON
XIN
XOUT
VARICAP
XTAL
OSC
VCO
Divider
Phase
Detector
Charge
Pump
L o+o p
Filter
VCO
(F_XiNx16)
Output
Divider
(1,2,4,8)
QBAR
Q
OE
Performance Tuner
47745 Fremont Blvd., Fremont, California 94538 Tel [phone] Fax [phone] www.phaselink.com Rev 11/30/05 Page 1