PL580-30 Datasheet, PDF (2/9 Pages) PhaseLink Corporation – 38MHz-640MHz Low Phase Noise VCXO

(Preliminary) PL580-30
38MHz-640MHz Low Phase Noise VCXO
OUTPUT ENABLE LOGICAL LEVELS
OUTSEL0^v
(Pad #25)
OUTSEL1^
(Pad #18)
Selected Output
0
0
LVDS
0
1
PECL (Default)
1
0
High Drive CMOS
1
1
Standard Drive CMOS
Note: For bonding convenience, ‘OUTSEL0’ incorporates an internal pull down resistor while ‘OUTSEL1’ incorporates an internal pull up resistor.
OUTPUT SELECTION AND ENABLE
OE_SEL^
(Pad #9)
OE_CTRL
(Pad #30)
0 (Default)
0
1
1 (Default)
0
1 (Default)
Pad #9: Bond to GND to set to “0”, bond to VDD to set to “1”,
Pad #30: Logical states defined by PECL levels if OE_SELECT is “0”
Logical states defined by CMOS levels if OE_SELECT is “1”
State
Output enabled
Tri-state
Tri-state
Output enabled
FREQUENCY SELECTION TABLE
SEL2
SEL1
SEL0
Selected Multiplier/Output Frequency
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
All SEL pads have internal pull-ups (default value is ‘1’). Bond to GND to set to 0.
* Special Test Modes to help selecting the inductor value for the target output frequency.
VCO Max*
VCO Min*
Reserved
Reserved
Fin x 2
Fin x 8
Fin x 16
Fin x 4
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